commit 69356489fe43ca36f5ed20b7b92dc2cd0641803d
author Angel Pons <th3fanbus@gmail.com> Mon Aug 03 15:16:12 2020 +0200
committer Angel Pons <th3fanbus@gmail.com> Tue Aug 04 21:26:49 2020 +0000
tree 63f2cb44d262215c7a278b97130e69d215070f89
parent 92e4ca6a38a4f4c0cb772b9694e2d20ada254a46

nb/intel/pineview: Use `MiB` definition

Also constify a local variable while we're at it.

Tested with BUILD_TIMELESS=1, Foxconn D41S does not change.

Change-Id: I90ab35932d7c0ba99ca16732b9616f3a15d972dd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

src/northbridge/intel/pineview/acpi.c

diff --git a/src/northbridge/intel/pineview/acpi.c b/src/northbridge/intel/pineview/acpi.c
index 5becf8dc..2edd462 100644
--- a/src/northbridge/intel/pineview/acpi.c
+++ b/src/northbridge/intel/pineview/acpi.c
@@ -2,6 +2,7 @@
 
 #include <acpi/acpigen.h>
 #include <acpi/acpi.h>
+#include <commonlib/helpers.h>
 #include <device/device.h>
 #include <northbridge/intel/pineview/pineview.h>
 #include <types.h>
@@ -9,12 +10,11 @@
 unsigned long acpi_fill_mcfg(unsigned long current)
 {
 	u32 length, pciexbar;
-	int max_buses;
 
 	if (!decode_pciebar(&pciexbar, &length))
 		return current;
 
-	max_buses = length >> 20;
+	const int max_buses = length / MiB;
 	current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, pciexbar, 0, 0,
 			max_buses - 1);
 

src/northbridge/intel/pineview/memmap.c

diff --git a/src/northbridge/intel/pineview/memmap.c b/src/northbridge/intel/pineview/memmap.c
index ad89aef..bcf1487 100644
--- a/src/northbridge/intel/pineview/memmap.c
+++ b/src/northbridge/intel/pineview/memmap.c
@@ -3,6 +3,7 @@
 #define __SIMPLE_DEVICE__
 
 #include <arch/romstage.h>
+#include <commonlib/helpers.h>
 #include <device/pci_ops.h>
 #include <device/device.h>
 #include <device/pci_def.h>
@@ -51,7 +52,7 @@
 	}
 
 	*base = pciexbar;
-	*len = max_buses << 20;
+	*len = max_buses * MiB;
 	return 1;
 }
 
@@ -87,11 +88,11 @@
 
 	switch ((esmramc >> 1) & 3) {
 	case 0:
-		return 1 << 20;
+		return 1 * MiB;
 	case 1:
-		return 2 << 20;
+		return 2 * MiB;
 	case 2:
-		return 8 << 20;
+		return 8 * MiB;
 	case 3:
 	default:
 		die("Bad TSEG setting.\n");

src/northbridge/intel/pineview/northbridge.c

diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c
index 856eab3..e005bc9 100644
--- a/src/northbridge/intel/pineview/northbridge.c
+++ b/src/northbridge/intel/pineview/northbridge.c
@@ -18,7 +18,7 @@
  * 0xc0000 - 0xcffff: VGA OPROM (needed by kernel)
  * 0xe0000 - 0xfffff: SeaBIOS, if used, otherwise DMI
  */
-static const int legacy_hole_base_k = 0xa0000 / 1024;
+static const int legacy_hole_base_k = 0xa0000 / KiB;
 
 static void add_fixed_resources(struct device *dev, int index)
 {
@@ -33,8 +33,8 @@
 			| IORESOURCE_STORED
 			| IORESOURCE_ASSIGNED;
 
-	mmio_resource(dev, index++, legacy_hole_base_k, (0xc0000 >> 10) - legacy_hole_base_k);
-	reserved_ram_resource(dev, index++, 0xc0000 >> 10, (0x100000 - 0xc0000) >> 10);
+	mmio_resource(dev, index++, legacy_hole_base_k, (0xc0000 / KiB) - legacy_hole_base_k);
+	reserved_ram_resource(dev, index++, 0xc0000 / KiB, (0x100000 - 0xc0000) / KiB);
 }
 
 static void mch_domain_read_resources(struct device *dev)