commit 6935350ad6610fca943afc4ae96125760538f98c
author Maulik V Vaghela <maulik.v.vaghela@intel.com> Wed Apr 14 14:01:02 2021 +0530
committer Patrick Georgi <pgeorgi@google.com> Fri Apr 16 06:44:28 2021 +0000
tree 74fddae9ea7c1f6d79c09821a04aa6ec8486264d
parent ba0ab9f1f52f64906beaa6ebf079864b07f6f43e

soc/intel/alderlake: Allow devicetree to fill UPD related to TCSS OC

We need to change OC pin for type C USB3 ports and it depends
on the board design. Allowing it to be filled by devicetree will
make it easier to change the mapping based on the board design

BUG=b:184653645
BRANCH=None
TEST=compilation works fine and value of UPD is getting reflected.

Change-Id: I61faa661c12dced27c6cdd7005a61ae8de8621e1
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52320
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>

src/soc/intel/alderlake/chip.h

diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index 164d1b9..f7412dc 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -9,6 +9,7 @@
 #include <intelblocks/gspi.h>
 #include <intelblocks/power_limit.h>
 #include <intelblocks/pcie_rp.h>
+#include <intelblocks/tcss.h>
 #include <soc/gpe.h>
 #include <soc/pci_devs.h>
 #include <soc/pmc.h>
@@ -87,6 +88,8 @@
 	uint16_t usb2_wake_enable_bitmap;
 	/* Wake Enable Bitmap for USB3 ports */
 	uint16_t usb3_wake_enable_bitmap;
+	/* Program OC pins for TCSS */
+	struct tcss_port_config tcss_ports[MAX_TYPE_C_PORTS];
 
 	/* SATA related */
 	uint8_t SataEnable;

src/soc/intel/alderlake/fsp_params.c

diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index 19afbc4..2ab1825 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -184,6 +184,11 @@
 		}
 	}
 
+	for (i = 0; i < ARRAY_SIZE(config->tcss_ports); i++) {
+		if (config->tcss_ports[i].enable)
+			params->CpuUsb3OverCurrentPin[i] = config->tcss_ports[i].ocpin;
+	}
+
 	/* Enable xDCI controller if enabled in devicetree and allowed */
 	dev = pcidev_path_on_root(PCH_DEVFN_USBOTG);
 	if (dev) {

src/soc/intel/alderlake/include/soc/usb.h

diff --git a/src/soc/intel/alderlake/include/soc/usb.h b/src/soc/intel/alderlake/include/soc/usb.h
index 846849a..e339c72 100644
--- a/src/soc/intel/alderlake/include/soc/usb.h
+++ b/src/soc/intel/alderlake/include/soc/usb.h
@@ -135,4 +135,20 @@
 	.tx_downscale_amp = 0x00, \
 }
 
+struct tcss_port_config {
+	uint8_t enable;
+	uint8_t ocpin;
+};
+
+#define TCSS_PORT_EMPTY { \
+	.enable           = 0, \
+	.ocpin            = OC_SKIP, \
+}
+
+#define TCSS_PORT_DEFAULT(pin) { \
+	.enable           = 1, \
+	.ocpin            = (pin), \
+}
+
+
 #endif