rockchip/rk3288: add support for hdmi display
this is an brief hdmi driver which config with simple
display parameter, const encoder input & output color
format and 8bit color depth, and only 48KHz audio support.
what's more to prevent TV have not show an right things
before coreboot switch to kernel space, we have to add
an terrible 2s delay to driver (2s come from test many
times), cause we have to wait TV to respond (we got no
flag to check whether it is ready).
BUG=chrome-os-partner:40337
TEST=Booted Veyron Jerry and display normal
BRANCH=None
Change-Id: Icd33467e95de6219e1b614616f0112afc52097b6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7e5b699aff75a579116aae63d858c834b2f648e8
Original-Change-Id: Iedc87c011c5b62ce5f16a296dd9c3e0c2eaba59b
Original-Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/272565
Original-Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Original-Commit-Queue: Lin Huang <hl@rock-chips.com>
Original-Tested-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: http://review.coreboot.org/10625
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
diff --git a/src/soc/rockchip/rk3288/vop.c b/src/soc/rockchip/rk3288/vop.c
index 04a7b0f..03338e8 100644
--- a/src/soc/rockchip/rk3288/vop.c
+++ b/src/soc/rockchip/rk3288/vop.c
@@ -96,7 +96,7 @@
write32(&preg->reg_cfg_done, 0x01); /* enable reg config */
}
-void rkvop_mode_set(u32 vop_id, const struct edid *edid)
+void rkvop_mode_set(u32 vop_id, const struct edid *edid, u32 mode)
{
u32 hactive = edid->ha;
u32 vactive = edid->va;
@@ -108,9 +108,26 @@
u32 vback_porch = edid->vbl - edid->vso - edid->vspw;
struct rk3288_vop_regs *preg = vop_regs[vop_id];
- clrsetbits_le32(&preg->sys_ctrl, M_ALL_OUT_EN, V_EDP_OUT_EN(1));
- clrsetbits_le32(&preg->dsp_ctrl0, M_DSP_OUT_MODE,
- V_DSP_OUT_MODE(15));
+ switch (mode) {
+
+ case HDMI_MODE:
+ clrsetbits_le32(&preg->sys_ctrl,
+ M_ALL_OUT_EN, V_HDMI_OUT_EN(1));
+ break;
+
+ case EDP_MODE:
+ default:
+ clrsetbits_le32(&preg->sys_ctrl,
+ M_ALL_OUT_EN, V_EDP_OUT_EN(1));
+ break;
+ }
+
+ clrsetbits_le32(&preg->dsp_ctrl0,
+ M_DSP_OUT_MODE | M_DSP_VSYNC_POL | M_DSP_HSYNC_POL,
+ V_DSP_OUT_MODE(15) |
+ V_DSP_HSYNC_POL(!!edid->phsync) |
+ V_DSP_VSYNC_POL(!!edid->pvsync));
+
write32(&preg->dsp_htotal_hs_end, V_HSYNC(hsync_len) |
V_HORPRD(hsync_len + hback_porch + hactive + hfront_porch));