soc/amd/picasso: add UPD for RV2 USB3 phy setting adjust
add UPD for RV2 USB3 phy setting adjust.
Note: it only for RV2 silicon and not available for RV/PCO.
Usb 3.1 PHY Parameters:
1. RX_EQ_DELTA_IQ_OVRD_VAL
-Override value for rx_eq_delta_iq. Range 0-0xF
2. RX_EQ_DELTA_IQ_OVRD_EN
-Enable override value for rx_eq_delta_iq. Range 0-0x1
3. Override value for rx_vref_ctrl. Range 0 - 0x1F
4. Enable override value for rx_vref_ctrl. Range 0 - 0x1
5. Override value for tx_vboost_lvl: 0 - 0x7.
6. Enable override value for tx_vboost_lvl. Range: 0 - 0x1
7. Override value for rx_vref_ctrl. Range 0 - 0x1F
8. Enable override value for rx_vref_ctrl. Range 0 - 0x1
9. Override value for tx_vboost_lvl: 0 - 0x7.
10. Enable override value for tx_vboost_lvl. Range: 0 - 0x1
BUG=b:175192931
TEST=Build/verify the valule will been apply on dirinboz
Change-Id: I1d5f69e840952cc5171af1ce8597628d1bede5cb
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50240
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb
index e014ce3..9b0dd9a 100644
--- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb
+++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb
@@ -134,6 +134,47 @@
.tx_res_tune = 0x01,
}"
+ # Start RV2 USB3 PHY Parameters
+ register "usb3_phy_override" = "0"
+
+ # USB3 Port0 Default
+ register "usb3_phy_tune_params[0]" = "{
+ .rx_eq_delta_iq_ovrd_val = 0x0,
+ .rx_eq_delta_iq_ovrd_en = 0x0,
+ }"
+
+ # USB3 Port1 Default
+ register "usb3_phy_tune_params[1]" = "{
+ .rx_eq_delta_iq_ovrd_val = 0x0,
+ .rx_eq_delta_iq_ovrd_en = 0x0,
+ }"
+
+ # USB3 Port2 Default
+ register "usb3_phy_tune_params[2]" = "{
+ .rx_eq_delta_iq_ovrd_val = 0x0,
+ .rx_eq_delta_iq_ovrd_en = 0x0,
+ }"
+
+ # USB3 Port3 Default
+ register "usb3_phy_tune_params[3]" = "{
+ .rx_eq_delta_iq_ovrd_val = 0x0,
+ .rx_eq_delta_iq_ovrd_en = 0x0,
+ }"
+
+ # SUP_DIG_LVL_OVRD_IN Default
+ register "usb3_rx_vref_ctrl" = "0x10"
+ register "usb3_rx_vref_ctrl_en" = "0x00"
+ register "usb_3_tx_vboost_lvl" = "0x07"
+ register "usb_3_tx_vboost_lvl_en" = "0x00"
+
+ # SUPX_DIG_LVL_OVRD_IN Default
+ register "usb_3_rx_vref_ctrl_x" = "0x10"
+ register "usb_3_rx_vref_ctrl_en_x" = "0x00"
+ register "usb_3_tx_vboost_lvl_x" = "0x07"
+ register "usb_3_tx_vboost_lvl_en_x" = "0x00"
+
+ # End RV2 USB3 phy setting
+
# USB OC pin mapping
register "usb_port_overcurrent_pin[0]" = "USB_OC_PIN_0" # USB C0
register "usb_port_overcurrent_pin[1]" = "USB_OC_PIN_1" # USB C1
diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb
index 5ec9010..a3c4573 100644
--- a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb
+++ b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb
@@ -134,6 +134,47 @@
.tx_res_tune = 0x01,
}"
+ # Start RV2 USB3 PHY Parameters
+ register "usb3_phy_override" = "0"
+
+ # USB3 Port0 Default
+ register "usb3_phy_tune_params[0]" = "{
+ .rx_eq_delta_iq_ovrd_val = 0x0,
+ .rx_eq_delta_iq_ovrd_en = 0x0,
+ }"
+
+ # USB3 Port1 Default
+ register "usb3_phy_tune_params[1]" = "{
+ .rx_eq_delta_iq_ovrd_val = 0x0,
+ .rx_eq_delta_iq_ovrd_en = 0x0,
+ }"
+
+ # USB3 Port2 Default
+ register "usb3_phy_tune_params[2]" = "{
+ .rx_eq_delta_iq_ovrd_val = 0x0,
+ .rx_eq_delta_iq_ovrd_en = 0x0,
+ }"
+
+ # USB3 Port3 Default
+ register "usb3_phy_tune_params[3]" = "{
+ .rx_eq_delta_iq_ovrd_val = 0x0,
+ .rx_eq_delta_iq_ovrd_en = 0x0,
+ }"
+
+ # SUP_DIG_LVL_OVRD_IN Default
+ register "usb3_rx_vref_ctrl" = "0x10"
+ register "usb3_rx_vref_ctrl_en" = "0x00"
+ register "usb_3_tx_vboost_lvl" = "0x07"
+ register "usb_3_tx_vboost_lvl_en" = "0x00"
+
+ # SUPX_DIG_LVL_OVRD_IN Default
+ register "usb_3_rx_vref_ctrl_x" = "0x10"
+ register "usb_3_rx_vref_ctrl_en_x" = "0x00"
+ register "usb_3_tx_vboost_lvl_x" = "0x07"
+ register "usb_3_tx_vboost_lvl_en_x" = "0x00"
+
+ # End RV2 USB3 phy setting
+
# SPI Configuration
register "common_config.spi_config" = "{
.normal_speed = SPI_SPEED_33M, /* MHz */
diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h
index 9a7d2a5..313b6c3 100644
--- a/src/soc/amd/picasso/chip.h
+++ b/src/soc/amd/picasso/chip.h
@@ -66,6 +66,13 @@
};
#define USB_PORT_COUNT 6
+
+struct __packed usb3_phy_tune {
+ uint8_t rx_eq_delta_iq_ovrd_val;
+ uint8_t rx_eq_delta_iq_ovrd_en;
+};
+/* the RV2 USB3 port count */
+#define RV2_USB3_PORT_COUNT 4
#define USB_PD_PORT_COUNT 2
enum sd_emmc_driver_strength {
@@ -247,6 +254,30 @@
USB_OC_NONE = 0xf,
} usb_port_overcurrent_pin[USB_PORT_COUNT];
+ /* RV2 SOC Usb 3.1 PHY Parameters */
+ uint8_t usb3_phy_override;
+ /*
+ * 1,RX_EQ_DELTA_IQ_OVRD_VAL- Override value for rx_eq_delta_iq. Range 0-0xF
+ * 2,RX_EQ_DELTA_IQ_OVRD_EN - Enable override value for rx_eq_delta_iq. Range 0-0x1
+ */
+ struct usb3_phy_tune usb3_phy_tune_params[RV2_USB3_PORT_COUNT];
+ /* Override value for rx_vref_ctrl. Range 0 - 0x1F */
+ uint8_t usb3_rx_vref_ctrl;
+ /* Enable override value for rx_vref_ctrl. Range 0 - 0x1 */
+ uint8_t usb3_rx_vref_ctrl_en;
+ /* Override value for tx_vboost_lvl: 0 - 0x7. */
+ uint8_t usb_3_tx_vboost_lvl;
+ /* Enable override value for tx_vboost_lvl. Range: 0 - 0x1 */
+ uint8_t usb_3_tx_vboost_lvl_en;
+ /* Override value for rx_vref_ctrl. Range 0 - 0x1F.*/
+ uint8_t usb_3_rx_vref_ctrl_x;
+ /* Enable override value for rx_vref_ctrl. Range 0 - 0x1. */
+ uint8_t usb_3_rx_vref_ctrl_en_x;
+ /* Override value for tx_vboost_lvl: 0 - 0x7. */
+ uint8_t usb_3_tx_vboost_lvl_x;
+ /* Enable override value for tx_vboost_lvl. Range: 0 - 0x1. */
+ uint8_t usb_3_tx_vboost_lvl_en_x;
+
/* The array index is the general purpose PCIe clock output number. */
enum gpp_clk_req_setting gpp_clk_config[GPP_CLK_OUTPUT_COUNT];
/* If using an external 48MHz OSC for codec, will disable internal X48M_OSC */
diff --git a/src/soc/amd/picasso/fsp_params.c b/src/soc/amd/picasso/fsp_params.c
index df5e1e6..e77cbde 100644
--- a/src/soc/amd/picasso/fsp_params.c
+++ b/src/soc/amd/picasso/fsp_params.c
@@ -5,6 +5,7 @@
#include <soc/iomap.h>
#include <soc/pci_devs.h>
#include <soc/platform_descriptors.h>
+#include <soc/soc_util.h>
#include <fsp/api.h>
#include "chip.h"
@@ -126,6 +127,23 @@
scfg->xhci_oc_pin_select |=
(cfg->usb_port_overcurrent_pin[i] & 0xf) << (i * 4);
}
+
+ if ((get_silicon_type() == SILICON_RV2) && cfg->usb3_phy_override) {
+ scfg->usb_3_phy_enable = cfg->usb3_phy_override;
+ for (i = 0; i < FSPS_UPD_RV2_USB3_PORT_COUNT; i++) {
+ memcpy(scfg->usb_3_port_phy_tune[i],
+ &cfg->usb3_phy_tune_params[i],
+ sizeof(scfg->usb_3_port_phy_tune[0]));
+ }
+ scfg->usb_3_rx_vref_ctrl = cfg->usb3_rx_vref_ctrl;
+ scfg->usb_3_rx_vref_ctrl_en = cfg->usb3_rx_vref_ctrl_en;
+ scfg->usb_3_tx_vboost_lvl = cfg->usb_3_tx_vboost_lvl;
+ scfg->usb_3_tx_vboost_lvl_en = cfg->usb_3_tx_vboost_lvl_en;
+ scfg->usb_3_rx_vref_ctrl_x = cfg->usb_3_rx_vref_ctrl_x;
+ scfg->usb_3_rx_vref_ctrl_en_x = cfg->usb_3_rx_vref_ctrl_en_x;
+ scfg->usb_3_tx_vboost_lvl_x = cfg->usb_3_tx_vboost_lvl_x;
+ scfg->usb_3_tx_vboost_lvl_en_x = cfg->usb_3_tx_vboost_lvl_en_x;
+ }
}
static void fsp_assign_ioapic_upds(FSP_S_CONFIG *scfg)
diff --git a/src/vendorcode/amd/fsp/picasso/FspsUpd.h b/src/vendorcode/amd/fsp/picasso/FspsUpd.h
index aac6fdb..f931bf0 100644
--- a/src/vendorcode/amd/fsp/picasso/FspsUpd.h
+++ b/src/vendorcode/amd/fsp/picasso/FspsUpd.h
@@ -12,6 +12,7 @@
#define FSPS_UPD_DXIO_DESCRIPTOR_COUNT 8
#define FSPS_UPD_DDI_DESCRIPTOR_COUNT 4
#define FSPS_UPD_USB2_PORT_COUNT 6
+#define FSPS_UPD_RV2_USB3_PORT_COUNT 4
typedef struct __packed {
/** Offset 0x0020**/ uint32_t emmc0_mode;
@@ -54,7 +55,17 @@
/** Offset 0x0139**/ uint8_t pwron_varybl_to_blon;
/** Offset 0x013A**/ uint8_t pwrdown_bloff_to_varybloff;
/** Offset 0x013B**/ uint8_t min_allowed_bl_level;
- /** Offset 0x013C**/ uint8_t UnusedUpdSpace0[20];
+ /** Offset 0x013C**/ uint8_t usb_3_phy_enable;
+ /** Offset 0x013D**/ uint8_t usb_3_port_phy_tune[FSPS_UPD_RV2_USB3_PORT_COUNT][2];
+ /** Offset 0x0145**/ uint8_t usb_3_rx_vref_ctrl;
+ /** Offset 0x0146**/ uint8_t usb_3_rx_vref_ctrl_en;
+ /** Offset 0x0147**/ uint8_t usb_3_tx_vboost_lvl;
+ /** Offset 0x0148**/ uint8_t usb_3_tx_vboost_lvl_en;
+ /** Offset 0x0149**/ uint8_t usb_3_rx_vref_ctrl_x;
+ /** Offset 0x014A**/ uint8_t usb_3_rx_vref_ctrl_en_x;
+ /** Offset 0x014B**/ uint8_t usb_3_tx_vboost_lvl_x;
+ /** Offset 0x014C**/ uint8_t usb_3_tx_vboost_lvl_en_x;
+ /** Offset 0x014D**/ uint8_t UnusedUpdSpace0[3];
/** Offset 0x0150**/ uint16_t UpdTerminator;
} FSP_S_CONFIG;