src: Get rid of device_t
Use of device_t is deprecated.
Change-Id: I6adc0429ae9ecc8f726d6167a6458d9333dc515f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
diff --git a/src/lib/debug.c b/src/lib/debug.c
index 6ae5985..80ee416 100644
--- a/src/lib/debug.c
+++ b/src/lib/debug.c
@@ -22,7 +22,11 @@
static inline void print_pci_devices(void)
{
- device_t dev;
+#if defined(__SIMPLE_DEVICE__)
+ pci_devfn_t dev;
+#else
+ struct device *dev;
+#endif
for (dev = PCI_DEV(0, 0, 0);
dev <= PCI_DEV(0x00, 0x1f, 0x7); dev += PCI_DEV(0, 0, 1)) {
u32 id;
@@ -56,7 +60,11 @@
static inline void dump_pci_devices(void)
{
- device_t dev;
+#if defined(__SIMPLE_DEVICE__)
+ pci_devfn_t dev;
+#else
+ struct device *dev;
+#endif
for (dev = PCI_DEV(0, 0, 0);
dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0, 0, 1)) {
u32 id;
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
index 4100b26..a351e8d 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
@@ -70,9 +70,9 @@
if (is_fam15h()) {
uint32_t dword;
#ifdef __PRE_RAM__
- device_t dev_fn1 = PCI_DEV(0, 0x18 + node, 1);
+ pci_devfn_t dev_fn1 = PCI_DEV(0, 0x18 + node, 1);
#else
- device_t dev_fn1 = dev_find_slot(0, PCI_DEVFN(0x18 + node, 1));
+ struct device *dev_fn1 = dev_find_slot(0, PCI_DEVFN(0x18 + node, 1));
#endif
/* Select DCT */
@@ -92,9 +92,9 @@
if (is_fam15h()) {
uint32_t dword;
#ifdef __PRE_RAM__
- device_t dev_fn1 = PCI_DEV(0, 0x18 + node, 1);
+ pci_devfn_t dev_fn1 = PCI_DEV(0, 0x18 + node, 1);
#else
- device_t dev_fn1 = dev_find_slot(0, PCI_DEVFN(0x18 + node, 1));
+ struct device *dev_fn1 = dev_find_slot(0, PCI_DEVFN(0x18 + node, 1));
#endif
/* Select DCT */
@@ -129,9 +129,9 @@
if (is_fam15h()) {
uint32_t dword;
#ifdef __PRE_RAM__
- device_t dev_fn1 = PCI_DEV(0, 0x18 + node, 1);
+ pci_devfn_t dev_fn1 = PCI_DEV(0, 0x18 + node, 1);
#else
- device_t dev_fn1 = dev_find_slot(0, PCI_DEVFN(0x18 + node, 1));
+ struct device *dev_fn1 = dev_find_slot(0, PCI_DEVFN(0x18 + node, 1));
#endif
/* Select DCT */
@@ -247,9 +247,12 @@
return (((uint64_t)msr.hi) << 32) | ((uint64_t)msr.lo);
}
-static uint32_t read_config32_dct_nbpstate(device_t dev, uint8_t node, uint8_t dct, uint8_t nb_pstate, uint32_t reg) {
+static uint32_t read_config32_dct_nbpstate(struct device *dev, uint8_t node,
+ uint8_t dct, uint8_t nb_pstate,
+ uint32_t reg)
+{
uint32_t dword;
- device_t dev_fn1 = dev_find_slot(0, PCI_DEVFN(0x18 + node, 1));
+ struct device *dev_fn1 = dev_find_slot(0, PCI_DEVFN(0x18 + node, 1));
/* Select DCT */
dword = pci_read_config32(dev_fn1, 0x10c);
@@ -312,9 +315,9 @@
/* Load data from DCTs into data structure */
for (node = 0; node < MAX_NODES_SUPPORTED; node++) {
- device_t dev_fn1 = dev_find_slot(0, PCI_DEVFN(0x18 + node, 1));
- device_t dev_fn2 = dev_find_slot(0, PCI_DEVFN(0x18 + node, 2));
- device_t dev_fn3 = dev_find_slot(0, PCI_DEVFN(0x18 + node, 3));
+ struct device *dev_fn1 = dev_find_slot(0, PCI_DEVFN(0x18 + node, 1));
+ struct device *dev_fn2 = dev_find_slot(0, PCI_DEVFN(0x18 + node, 2));
+ struct device *dev_fn3 = dev_find_slot(0, PCI_DEVFN(0x18 + node, 3));
/* Test for node presence */
if ((!dev_fn1) || (pci_read_config32(dev_fn1, PCI_VENDOR_ID) == 0xffffffff)) {
persistent_data->node[node].node_present = 0;
@@ -524,9 +527,12 @@
}
}
#else
-static void write_config32_dct_nbpstate(device_t dev, uint8_t node, uint8_t dct, uint8_t nb_pstate, uint32_t reg, uint32_t value) {
+static void write_config32_dct_nbpstate(pci_devfn_t dev, uint8_t node,
+ uint8_t dct, uint8_t nb_pstate,
+ uint32_t reg, uint32_t value)
+{
uint32_t dword;
- device_t dev_fn1 = PCI_DEV(0, 0x18 + node, 1);
+ pci_devfn_t dev_fn1 = PCI_DEV(0, 0x18 + node, 1);
/* Select DCT */
dword = pci_read_config32(dev_fn1, 0x10c);
@@ -543,7 +549,9 @@
pci_write_config32(dev, reg, value);
}
-static void write_amd_dct_index_register(device_t dev, uint32_t index_ctl_reg, uint32_t index, uint32_t value)
+static void write_amd_dct_index_register(pci_devfn_t dev,
+ uint32_t index_ctl_reg, uint32_t index,
+ uint32_t value)
{
uint32_t dword;
@@ -555,11 +563,14 @@
} while (!(dword & (1 << 31)));
}
-static void write_amd_dct_index_register_dct(device_t dev, uint8_t node, uint8_t dct, uint32_t index_ctl_reg, uint32_t index, uint32_t value)
+static void write_amd_dct_index_register_dct(pci_devfn_t dev, uint8_t node,
+ uint8_t dct,
+ uint32_t index_ctl_reg,
+ uint32_t index, uint32_t value)
{
if (is_fam15h()) {
uint32_t dword;
- device_t dev_fn1 = PCI_DEV(0, 0x18 + node, 1);
+ pci_devfn_t dev_fn1 = PCI_DEV(0, 0x18 + node, 1);
/* Select DCT */
dword = pci_read_config32(dev_fn1, 0x10c);
diff --git a/src/soc/intel/apollolake/uart.c b/src/soc/intel/apollolake/uart.c
index 54b280d..a59b567 100644
--- a/src/soc/intel/apollolake/uart.c
+++ b/src/soc/intel/apollolake/uart.c
@@ -60,7 +60,11 @@
void pch_uart_init(void)
{
uintptr_t base = CONFIG_CONSOLE_UART_BASE_ADDRESS;
- device_t uart = _PCH_DEV(UART, CONFIG_UART_FOR_CONSOLE & 3);
+#if defined(__SIMPLE_DEVICE__)
+ pci_devfn_t uart = _PCH_DEV(UART, CONFIG_UART_FOR_CONSOLE & 3);
+#else
+ struct device *uart = _PCH_DEV(UART, CONFIG_UART_FOR_CONSOLE & 3);
+#endif
/* Get a 0-based pad index. See invalid_uart_for_console() above. */
const int pad_index = CONFIG_UART_FOR_CONSOLE - 1;
diff --git a/src/soc/intel/broadwell/pmutil.c b/src/soc/intel/broadwell/pmutil.c
index 25624cc..3899130 100644
--- a/src/soc/intel/broadwell/pmutil.c
+++ b/src/soc/intel/broadwell/pmutil.c
@@ -452,7 +452,11 @@
{
u8 reg8;
int rtc_failed;
- device_t dev = PCH_DEV_LPC;
+#if defined(__SIMPLE_DEVICE__)
+ pci_devfn_t dev = PCH_DEV_LPC;
+#else
+ struct device *dev = PCH_DEV_LPC;
+#endif
reg8 = pci_read_config8(dev, GEN_PMCON_3);
rtc_failed = reg8 & RTC_BATTERY_DEAD;
diff --git a/src/soc/intel/broadwell/romstage/uart.c b/src/soc/intel/broadwell/romstage/uart.c
index 1ea7cc2..abc4a47 100644
--- a/src/soc/intel/broadwell/romstage/uart.c
+++ b/src/soc/intel/broadwell/romstage/uart.c
@@ -48,7 +48,11 @@
{
/* Program IOBP CB000154h[12,9:8,4:0] = 1001100011111b */
u32 gpiodf = 0x131f;
- device_t dev;
+#if defined(__SIMPLE_DEVICE__)
+ pci_devfn_t dev;
+#else
+ struct device *dev;
+#endif
/* Put UART in byte access mode for 16550 compatibility */
switch (CONFIG_INTEL_PCH_UART_CONSOLE_NUMBER) {
diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c
index 0b8a970..24f6a3d 100644
--- a/src/soc/intel/broadwell/smihandler.c
+++ b/src/soc/intel/broadwell/smihandler.c
@@ -80,7 +80,11 @@
for (slot = 0; slot < 0x20; slot++) {
for (func = 0; func < 8; func++) {
u32 reg32;
- device_t dev = PCI_DEV(bus, slot, func);
+#if defined(__SIMPLE_DEVICE__)
+ pci_devfn_t dev = PCI_DEV(bus, slot, func);
+#else
+ struct device *dev = PCI_DEV(bus, slot, func);
+#endif
val = pci_read_config32(dev, PCI_VENDOR_ID);
diff --git a/src/soc/intel/broadwell/spi.c b/src/soc/intel/broadwell/spi.c
index 7a764f1..7d862f2 100644
--- a/src/soc/intel/broadwell/spi.c
+++ b/src/soc/intel/broadwell/spi.c
@@ -266,7 +266,11 @@
uint8_t *rcrb; /* Root Complex Register Block */
uint32_t rcba; /* Root Complex Base Address */
uint8_t bios_cntl;
- device_t dev = PCH_DEV_LPC;
+#if defined(__SIMPLE_DEVICE__)
+ pci_devfn_t dev = PCH_DEV_LPC;
+#else
+ struct device *dev = PCH_DEV_LPC;
+#endif
ich9_spi_regs *ich9_spi;
pci_read_config_dword(dev, 0xf0, &rcba);
diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c
index 69a921f..d399d1b 100644
--- a/src/soc/intel/cannonlake/lpc.c
+++ b/src/soc/intel/cannonlake/lpc.c
@@ -140,8 +140,11 @@
pch_interrupt_routing[7] = config->pirqh_routing;
itss_irq_init(pch_interrupt_routing);
-
- device_t irq_dev;
+#if defined(__SIMPLE_DEVICE__)
+ pci_devfn_t irq_dev;
+#else
+ struct device *irq_dev;
+#endif
for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
u8 int_pin = 0, int_line = 0;
diff --git a/src/soc/intel/cannonlake/uart.c b/src/soc/intel/cannonlake/uart.c
index 6aad685..8040410 100644
--- a/src/soc/intel/cannonlake/uart.c
+++ b/src/soc/intel/cannonlake/uart.c
@@ -35,7 +35,11 @@
static const struct port {
struct pad_config pads[2]; /* just TX and RX */
- device_t dev;
+#if defined(__SIMPLE_DEVICE__)
+ pci_devfn_t dev;
+#else
+ struct device *dev;
+#endif
} uart_ports[] = {
{.dev = PCH_DEV_UART0,
.pads = { PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* RX */
diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c
index 02ab886..01a4928 100644
--- a/src/soc/intel/common/block/acpi/acpi.c
+++ b/src/soc/intel/common/block/acpi/acpi.c
@@ -164,7 +164,7 @@
soc_fill_fadt(fadt);
}
-unsigned long southbridge_write_acpi_tables(device_t device,
+unsigned long southbridge_write_acpi_tables(struct device *device,
unsigned long current,
struct acpi_rsdp *rsdp)
{
@@ -224,7 +224,7 @@
{
}
-void southbridge_inject_dsdt(device_t device)
+void southbridge_inject_dsdt(struct device *device)
{
struct global_nvs_t *gnvs;
@@ -407,7 +407,7 @@
{
}
-void generate_cpu_entries(device_t device)
+void generate_cpu_entries(struct device *device)
{
int core_id, cpu_id, pcontrol_blk = ACPI_BASE_ADDRESS;
int plen = 6;
diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c
index 97ad176..e264348 100644
--- a/src/soc/intel/common/block/cpu/mp_init.c
+++ b/src/soc/intel/common/block/cpu/mp_init.c
@@ -31,7 +31,7 @@
static const void *microcode_patch;
/* SoC override function */
-__weak void soc_core_init(device_t dev)
+__weak void soc_core_init(struct device *dev)
{
/* no-op */
}
@@ -41,7 +41,7 @@
/* no-op */
}
-static void init_one_cpu(device_t dev)
+static void init_one_cpu(struct device *dev)
{
soc_core_init(dev);
intel_microcode_load_unlocked(microcode_patch);
@@ -121,7 +121,7 @@
static void init_cpus(void *unused)
{
- device_t dev = dev_find_path(NULL, DEVICE_PATH_CPU_CLUSTER);
+ struct device *dev = dev_find_path(NULL, DEVICE_PATH_CPU_CLUSTER);
assert(dev != NULL);
microcode_patch = intel_microcode_find();
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c
index 4991db6..8651297 100644
--- a/src/soc/intel/common/block/cse/cse.c
+++ b/src/soc/intel/common/block/cse/cse.c
@@ -80,7 +80,11 @@
void heci_init(uintptr_t tempbar)
{
struct cse_device *cse = car_get_var_ptr(&g_cse);
- device_t dev = PCH_DEV_CSE;
+#if defined(__SIMPLE_DEVICE__)
+ pci_devfn_t dev = PCH_DEV_CSE;
+#else
+ struct device *dev = PCH_DEV_CSE;
+#endif
u8 pcireg;
/* Assume it is already initialized, nothing else to do */
diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c
index b13408a..e7f81fc 100644
--- a/src/soc/intel/common/block/fast_spi/fast_spi.c
+++ b/src/soc/intel/common/block/fast_spi/fast_spi.c
@@ -34,7 +34,11 @@
*/
void *fast_spi_get_bar(void)
{
- device_t dev = PCH_DEV_SPI;
+#if defined(__SIMPLE_DEVICE__)
+ pci_devfn_t dev = PCH_DEV_SPI;
+#else
+ struct device *dev = PCH_DEV_SPI;
+#endif
uintptr_t bar;
bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
@@ -51,7 +55,11 @@
*/
void fast_spi_init(void)
{
- device_t dev = PCH_DEV_SPI;
+#if defined(__SIMPLE_DEVICE__)
+ pci_devfn_t dev = PCH_DEV_SPI;
+#else
+ struct device *dev = PCH_DEV_SPI;
+#endif
uint8_t bios_cntl;
bios_cntl = pci_read_config8(dev, SPIBAR_BIOS_CONTROL);
@@ -71,7 +79,11 @@
*/
static void fast_spi_set_bios_control_reg(uint8_t bios_cntl_bit)
{
- device_t dev = PCH_DEV_SPI;
+#if defined(__SIMPLE_DEVICE__)
+ pci_devfn_t dev = PCH_DEV_SPI;
+#else
+ struct device *dev = PCH_DEV_SPI;
+#endif
uint8_t bc_cntl;
assert((bios_cntl_bit & (bios_cntl_bit - 1)) == 0);
@@ -253,7 +265,11 @@
*/
void fast_spi_early_init(uintptr_t spi_base_address)
{
- device_t dev = PCH_DEV_SPI;
+#if defined(__SIMPLE_DEVICE__)
+ pci_devfn_t dev = PCH_DEV_SPI;
+#else
+ struct device *dev = PCH_DEV_SPI;
+#endif
uint8_t pcireg;
/* Assign Resources to SPI Controller */
@@ -285,7 +301,11 @@
/* Enable SPI Write Protect. */
void fast_spi_enable_wp(void)
{
- device_t dev = PCH_DEV_SPI;
+#if defined(__SIMPLE_DEVICE__)
+ pci_devfn_t dev = PCH_DEV_SPI;
+#else
+ struct device *dev = PCH_DEV_SPI;
+#endif
uint8_t bios_cntl;
bios_cntl = pci_read_config8(dev, SPIBAR_BIOS_CONTROL);
diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c
index 58b588e..d27f877 100644
--- a/src/soc/intel/common/block/lpc/lpc_lib.c
+++ b/src/soc/intel/common/block/lpc/lpc_lib.c
@@ -167,7 +167,11 @@
*/
static void lpc_set_bios_control_reg(uint8_t bios_cntl_bit)
{
- device_t dev = PCH_DEV_LPC;
+#if defined(__SIMPLE_DEVICE__)
+ pci_devfn_t dev = PCH_DEV_LPC;
+#else
+ struct device *dev = PCH_DEV_LPC;
+#endif
uint8_t bc_cntl;
assert(IS_POWER_OF_2(bios_cntl_bit));
@@ -210,7 +214,11 @@
*/
void lpc_set_serirq_mode(enum serirq_mode mode)
{
- device_t dev = PCH_DEV_LPC;
+#if defined(__SIMPLE_DEVICE__)
+ pci_devfn_t dev = PCH_DEV_LPC;
+#else
+ struct device *dev = PCH_DEV_LPC;
+#endif
uint8_t scnt;
scnt = pci_read_config8(dev, LPC_SERIRQ_CTL);
diff --git a/src/soc/intel/common/block/pcr/pcr.c b/src/soc/intel/common/block/pcr/pcr.c
index cf50fdc..b8d798f 100644
--- a/src/soc/intel/common/block/pcr/pcr.c
+++ b/src/soc/intel/common/block/pcr/pcr.c
@@ -254,7 +254,11 @@
int pcr_execute_sideband_msg(struct pcr_sbi_msg *msg, uint32_t *data,
uint8_t *response)
{
- device_t dev = PCH_DEV_P2SB;
+#if defined(__SIMPLE_DEVICE__)
+ pci_devfn_t dev = PCH_DEV_P2SB;
+#else
+ struct device *dev = PCH_DEV_P2SB;
+#endif
uint32_t sbi_data;
uint16_t sbi_status;
uint16_t sbi_rid;
diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c
index d8ac2f3..b49f2a3 100644
--- a/src/soc/intel/common/block/smm/smihandler.c
+++ b/src/soc/intel/common/block/smm/smihandler.c
@@ -134,7 +134,11 @@
for (slot = 0; slot < 0x20; slot++) {
for (func = 0; func < 8; func++) {
u32 reg32;
- device_t dev = PCI_DEV(bus, slot, func);
+#if defined(__SIMPLE_DEVICE__)
+ pci_devfn_t dev = PCI_DEV(bus, slot, func);
+#else
+ struct device *dev = PCI_DEV(bus, slot, func);
+#endif
if (!smihandler_soc_disable_busmaster(dev))
continue;
diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c
index cdbe56b..b84a7ec 100644
--- a/src/soc/intel/common/block/uart/uart.c
+++ b/src/soc/intel/common/block/uart/uart.c
@@ -59,7 +59,11 @@
bool uart_debug_controller_is_initialized(void)
{
- device_t dev;
+#if defined(__SIMPLE_DEVICE__)
+ pci_devfn_t dev;
+#else
+ struct device *dev;
+#endif
uintptr_t base;
dev = pch_uart_get_debug_controller();
diff --git a/src/soc/intel/denverton_ns/bootblock/uart.c b/src/soc/intel/denverton_ns/bootblock/uart.c
index 9af42ee..7d97661 100644
--- a/src/soc/intel/denverton_ns/bootblock/uart.c
+++ b/src/soc/intel/denverton_ns/bootblock/uart.c
@@ -31,8 +31,11 @@
u32 mmio_base)
{
register uint16_t reg16;
-
- device_t uart_dev = PCI_DEV(bus, dev, func);
+#if defined(__SIMPLE_DEVICE__)
+ pci_devfn_t uart_dev = PCI_DEV(bus, dev, func);
+#else
+ struct device *uart_dev = PCI_DEV(bus, dev, func);
+#endif
/* We're using MMIO for HSUARTs. This section is needed for logging
* from FSP only
diff --git a/src/soc/intel/denverton_ns/memmap.c b/src/soc/intel/denverton_ns/memmap.c
index 3fe41d2..813d5c6 100644
--- a/src/soc/intel/denverton_ns/memmap.c
+++ b/src/soc/intel/denverton_ns/memmap.c
@@ -30,8 +30,11 @@
/* Returns base of requested region encoded in the system agent. */
static inline uintptr_t system_agent_region_base(size_t reg)
{
- device_t dev = SA_DEV_ROOT;
-
+#if defined(__SIMPLE_DEVICE__)
+ pci_devfn_t dev = SA_DEV_ROOT;
+#else
+ struct device *dev = SA_DEV_ROOT;
+#endif
/* All regions concerned for have 1 MiB alignment. */
return ALIGN_DOWN(pci_read_config32(dev, reg), 1 * MiB);
}
diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c
index 105298e..3da349a 100644
--- a/src/soc/intel/denverton_ns/romstage.c
+++ b/src/soc/intel/denverton_ns/romstage.c
@@ -50,7 +50,11 @@
static void early_pmc_init(void)
{
/* PMC (B0:D31:F2). */
- device_t dev = PCH_PMC_DEV;
+#if defined(__SIMPLE_DEVICE__)
+ pci_devfn_t dev = PCH_PMC_DEV;
+#else
+ struct device *dev = PCH_PMC_DEV;
+#endif
/* Is PMC present */
if (pci_read_config16(dev, 0) == 0xffff) {
@@ -99,7 +103,11 @@
static void early_tco_init(void)
{
/* SMBUS (B0:D31:F4). */
- device_t dev = PCI_DEV(0, SMBUS_DEV, SMBUS_FUNC);
+#if defined(__SIMPLE_DEVICE__)
+ pci_devfn_t dev = PCI_DEV(0, SMBUS_DEV, SMBUS_FUNC);
+#else
+ struct device *dev = PCI_DEV(0, SMBUS_DEV, SMBUS_FUNC);
+#endif
/* Configure TCO base address */
if (pci_read_config16(dev, TCOBASE) == 0xffff) {
diff --git a/src/soc/intel/denverton_ns/smihandler.c b/src/soc/intel/denverton_ns/smihandler.c
index e434c1c..d97bc24 100644
--- a/src/soc/intel/denverton_ns/smihandler.c
+++ b/src/soc/intel/denverton_ns/smihandler.c
@@ -65,7 +65,11 @@
for (slot = 0; slot < 0x20; slot++) {
for (func = 0; func < 8; func++) {
u32 reg32;
- device_t dev = PCI_DEV(bus, slot, func);
+#if defined(__SIMPLE_DEVICE__)
+ pci_devfn_t dev = PCI_DEV(bus, slot, func);
+#else
+ struct device *dev = PCI_DEV(bus, slot, func);
+#endif
val = pci_read_config32(dev, PCI_VENDOR_ID);
diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c
index 521a1b7..ef61a60 100644
--- a/src/soc/intel/skylake/bootblock/pch.c
+++ b/src/soc/intel/skylake/bootblock/pch.c
@@ -46,7 +46,7 @@
static void enable_p2sbbar(void)
{
- device_t dev = PCH_DEV_P2SB;
+ pci_devfn_t dev = PCH_DEV_P2SB;
/* Enable PCR Base address in PCH */
pci_write_config32(dev, PCI_BASE_ADDRESS_0, CONFIG_PCR_BASE_ADDRESS);
diff --git a/src/soc/intel/skylake/bootblock/report_platform.c b/src/soc/intel/skylake/bootblock/report_platform.c
index 7473c57..8fd6599 100644
--- a/src/soc/intel/skylake/bootblock/report_platform.c
+++ b/src/soc/intel/skylake/bootblock/report_platform.c
@@ -104,12 +104,12 @@
{ PCI_DEVICE_ID_INTEL_KBL_GT2_DT2P2, "Kabylake DT GT2" },
};
-static uint8_t get_dev_revision(device_t dev)
+static uint8_t get_dev_revision(pci_devfn_t dev)
{
return pci_read_config8(dev, PCI_REVISION_ID);
}
-static uint16_t get_dev_id(device_t dev)
+static uint16_t get_dev_id(pci_devfn_t dev)
{
return pci_read_config16(dev, PCI_DEVICE_ID);
}
@@ -171,7 +171,7 @@
static void report_mch_info(void)
{
int i;
- device_t dev = SA_DEV_ROOT;
+ pci_devfn_t dev = SA_DEV_ROOT;
uint16_t mchid = get_dev_id(dev);
uint8_t mch_revision = get_dev_revision(dev);
const char *mch_type = "Unknown";
@@ -190,7 +190,7 @@
static void report_pch_info(void)
{
int i;
- device_t dev = PCH_DEV_LPC;
+ pci_devfn_t dev = PCH_DEV_LPC;
uint16_t lpcid = get_dev_id(dev);
const char *pch_type = "Unknown";
@@ -207,7 +207,7 @@
static void report_igd_info(void)
{
int i;
- device_t dev = SA_DEV_IGD;
+ pci_devfn_t dev = SA_DEV_IGD;
uint16_t igdid = get_dev_id(dev);
const char *igd_type = "Unknown";
diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c
index ecdc6bb..a2623d9 100644
--- a/src/soc/intel/skylake/pmc.c
+++ b/src/soc/intel/skylake/pmc.c
@@ -31,7 +31,11 @@
{
/* Set the DISB after DRAM init */
u32 disb_val;
- device_t dev = PCH_DEV_PMC;
+#if defined(__SIMPLE_DEVICE__)
+ pci_devfn_t dev = PCH_DEV_PMC;
+#else
+ struct device *dev = PCH_DEV_PMC;
+#endif
disb_val = pci_read_config32(dev, GEN_PMCON_A);
disb_val |= DISB;
diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c
index d05c812..2c399c7 100644
--- a/src/soc/intel/skylake/pmutil.c
+++ b/src/soc/intel/skylake/pmutil.c
@@ -19,8 +19,6 @@
* and the differences between PCH variants.
*/
-#define __SIMPLE_DEVICE__
-
#include <arch/acpi.h>
#include <arch/io.h>
#include <device/device.h>
@@ -232,7 +230,11 @@
u8 reg8;
int rtc_failed;
/* PMC Controller Device 0x1F, Func 02 */
- device_t dev = PCH_DEV_PMC;
+#if defined(__SIMPLE_DEVICE__)
+ pci_devfn_t dev = PCH_DEV_PMC;
+#else
+ struct device *dev = PCH_DEV_PMC;
+#endif
reg8 = pci_read_config8(dev, GEN_PMCON_B);
rtc_failed = reg8 & RTC_BATTERY_DEAD;
if (rtc_failed) {
diff --git a/src/southbridge/intel/bd82x6x/early_pch_common.c b/src/southbridge/intel/bd82x6x/early_pch_common.c
index 2ef47a2..f1ac4f0 100644
--- a/src/southbridge/intel/bd82x6x/early_pch_common.c
+++ b/src/southbridge/intel/bd82x6x/early_pch_common.c
@@ -66,9 +66,9 @@
int rtc_failure(void)
{
#if defined(__SIMPLE_DEVICE__)
- device_t dev = PCI_DEV(0, 0x1f, 0);
+ pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);
#else
- device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
+ struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
#endif
return !!(pci_read_config8(dev, GEN_PMCON_3) & RTC_BATTERY_DEAD);
}
diff --git a/src/southbridge/intel/bd82x6x/early_usb_mrc.c b/src/southbridge/intel/bd82x6x/early_usb_mrc.c
index 8fac3c7..4b9061e 100644
--- a/src/southbridge/intel/bd82x6x/early_usb_mrc.c
+++ b/src/southbridge/intel/bd82x6x/early_usb_mrc.c
@@ -32,8 +32,8 @@
*/
void enable_usb_bar(void)
{
- device_t usb0 = PCH_EHCI1_DEV;
- device_t usb1 = PCH_EHCI2_DEV;
+ pci_devfn_t usb0 = PCH_EHCI1_DEV;
+ pci_devfn_t usb1 = PCH_EHCI2_DEV;
u32 cmd;
/* USB Controller 1 */
diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c
index 73c84bb..7ff13a0 100644
--- a/src/southbridge/intel/bd82x6x/pch.c
+++ b/src/southbridge/intel/bd82x6x/pch.c
@@ -36,7 +36,7 @@
pci_devfn_t dev;
dev = PCI_DEV(0, 0x1f, 0);
#else
- device_t dev;
+ struct device *dev;
dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
#endif
@@ -53,7 +53,7 @@
pci_devfn_t dev;
dev = PCI_DEV(0, 0x1f, 0);
#else
- device_t dev;
+ struct device *dev;
dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
#endif
diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c
index bd89025..180a629 100644
--- a/src/southbridge/intel/common/spi.c
+++ b/src/southbridge/intel/common/spi.c
@@ -298,15 +298,14 @@
uint8_t *rcrb; /* Root Complex Register Block */
uint32_t rcba; /* Root Complex Base Address */
uint8_t bios_cntl;
- device_t dev;
ich9_spi_regs *ich9_spi;
ich7_spi_regs *ich7_spi;
uint16_t hsfs;
#ifdef __SIMPLE_DEVICE__
- dev = PCI_DEV(0, 31, 0);
+ pci_devfn_t dev = PCI_DEV(0, 31, 0);
#else
- dev = dev_find_slot(0, PCI_DEVFN(31, 0));
+ struct device *dev = dev_find_slot(0, PCI_DEVFN(31, 0));
#endif
pci_read_config_dword(dev, 0xf0, &rcba);
diff --git a/src/southbridge/intel/lynxpoint/pmutil.c b/src/southbridge/intel/lynxpoint/pmutil.c
index 00a6e65..e96d683 100644
--- a/src/southbridge/intel/lynxpoint/pmutil.c
+++ b/src/southbridge/intel/lynxpoint/pmutil.c
@@ -558,9 +558,9 @@
int rtc_failure(void)
{
#if defined(__SIMPLE_DEVICE__)
- device_t dev = PCI_DEV(0, 31, 0);
+ pci_devfn_t dev = PCI_DEV(0, 31, 0);
#else
- device_t dev = dev_find_slot(0, PCI_DEVFN(31, 0));
+ struct device *dev = dev_find_slot(0, PCI_DEVFN(31, 0));
#endif
return !!(pci_read_config8(dev, GEN_PMCON_3) & RTC_BATTERY_DEAD);
}
diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c
index dcec3f0..5cdd99d 100644
--- a/src/southbridge/intel/lynxpoint/smihandler.c
+++ b/src/southbridge/intel/lynxpoint/smihandler.c
@@ -75,7 +75,7 @@
for (slot = 0; slot < 0x20; slot++) {
for (func = 0; func < 8; func++) {
u32 reg32;
- device_t dev = PCI_DEV(bus, slot, func);
+ pci_devfn_t dev = PCI_DEV(bus, slot, func);
val = pci_read_config32(dev, PCI_VENDOR_ID);