tree 2b99cf49e67ad8c8f93cb9d84d5ea52a53cd410e
parent 39f9fbc57aeb60e65ec42d370d7ab76c0a4584d6
author Lijian Zhao <lijian.zhao@intel.com> 1553731601 -0700
committer Duncan Laurie <dlaurie@chromium.org> 1553741246 +0000

soc/intel/cannonlake: Update CPU Ratio base on MSR

The following is the FSP logic: as long as the Cpu Ratio input in
coreboot is different with CpuStrapSet, system will force to follow
input from coreboot. But CpuStrapsetting is floating, it will be 0
from the first cold boot before memory training and set to 0x1c (or
max CPU ratio for the installed CPU) after first memory training.

The previous fix was attempting to ensure settings were cleared
when FSP was called in recovery mode, but only when coming from S5
which caused issues if recovery mode is requested by the OS and
is only followed by a warm reset.

BUG=b:129412691
TEST=Boot up sarien platform and force recovery, check there's no reset
in the path of recovery.

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I959188be46343bc6f2cb3cc149097b4d449802aa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32089
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>