commit 682613f0653064eeeba2b4d15f6d50e32a692bd3
author Kyösti Mälkki <kyosti.malkki@gmail.com> Tue Jun 08 11:31:19 2021 +0300
committer Felix Held <felix-coreboot@felixheld.de> Fri Oct 22 14:16:38 2021 +0000
tree f53d9721eab49251b9ffda596f2b6d62e239e31d
parent ea6d12a0de8af000fb72a873b63364462f280643

sb,soc/intel: Replace set_ioapic_id() with setup_ioapic()

This adds delivery of PIC/i8259 interrupts via ExtNMI on the
affected platfoms.

Change-Id: If99e321fd9b153101d71e1b995b43dba48d8763f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

src/southbridge/intel/bd82x6x/lpc.c

diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index 51d6b07..ae92ca9 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -44,7 +44,7 @@
 	/* affirm full set of redirection table entries ("write once") */
 	ioapic_lock_max_vectors(VIO_APIC_VADDR);
 
-	set_ioapic_id(VIO_APIC_VADDR, 0x02);
+	setup_ioapic(VIO_APIC_VADDR, 0x02);
 }
 
 static void pch_enable_serial_irqs(struct device *dev)

src/southbridge/intel/i82371eb/isa.c

diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c
index 3d586bd..c2411f2b 100644
--- a/src/southbridge/intel/i82371eb/isa.c
+++ b/src/southbridge/intel/i82371eb/isa.c
@@ -61,7 +61,7 @@
 		pci_write_config16(dev, XBCS, reg16);
 
 		/* Set and verify the IOAPIC ID. */
-		set_ioapic_id(VIO_APIC_VADDR, ioapic_id);
+		setup_ioapic(VIO_APIC_VADDR, ioapic_id);
 		if (ioapic_id != get_ioapic_id(VIO_APIC_VADDR))
 			die("IOAPIC error!\n");
 	}

src/southbridge/intel/i82801dx/lpc.c

diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c
index 321c605..34d93c4 100644
--- a/src/southbridge/intel/i82801dx/lpc.c
+++ b/src/southbridge/intel/i82801dx/lpc.c
@@ -48,7 +48,7 @@
 	pci_write_config32(dev, GEN_CNTL, reg32);
 	printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32);
 
-	set_ioapic_id(VIO_APIC_VADDR, 0x02);
+	setup_ioapic(VIO_APIC_VADDR, 0x02);
 
 	ioapic_set_boot_config(VIO_APIC_VADDR, true);
 }

src/southbridge/intel/i82801gx/lpc.c

diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c
index ababe67..794d34a 100644
--- a/src/southbridge/intel/i82801gx/lpc.c
+++ b/src/southbridge/intel/i82801gx/lpc.c
@@ -33,7 +33,7 @@
  */
 static void i82801gx_enable_ioapic(struct device *dev)
 {
-	set_ioapic_id(VIO_APIC_VADDR, 0x02);
+	setup_ioapic(VIO_APIC_VADDR, 0x02);
 }
 
 static void i82801gx_enable_serial_irqs(struct device *dev)

src/southbridge/intel/ibexpeak/lpc.c

diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c
index fa53db2..01836b1 100644
--- a/src/southbridge/intel/ibexpeak/lpc.c
+++ b/src/southbridge/intel/ibexpeak/lpc.c
@@ -37,7 +37,7 @@
 	/* affirm full set of redirection table entries ("write once") */
 	ioapic_lock_max_vectors(VIO_APIC_VADDR);
 
-	set_ioapic_id(VIO_APIC_VADDR, 0x01);
+	setup_ioapic(VIO_APIC_VADDR, 0x01);
 }
 
 static void pch_enable_serial_irqs(struct device *dev)

src/southbridge/intel/lynxpoint/lpc.c

diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index 72f6d80..ea84def 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -42,7 +42,7 @@
 	else
 		ioapic_lock_max_vectors(VIO_APIC_VADDR);
 
-	set_ioapic_id(VIO_APIC_VADDR, 0x02);
+	setup_ioapic(VIO_APIC_VADDR, 0x02);
 
 }