Revert "mb/google/brya/var/kano: disabled autonomous GPIO power management"
This reverts commit 287cc02c007fd47b515d19389ea00ea0461fd5a1.
Reason for revert: it will break s0ix.
BUG=b:201266532
TEST=build pass
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I393077b26e2cdeae055d8eea1030754602e94ada
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
diff --git a/src/mainboard/google/brya/variants/kano/overridetree.cb b/src/mainboard/google/brya/variants/kano/overridetree.cb
index e650042..899dd36 100644
--- a/src/mainboard/google/brya/variants/kano/overridetree.cb
+++ b/src/mainboard/google/brya/variants/kano/overridetree.cb
@@ -15,17 +15,6 @@
chip soc/intel/alderlake
register "SaGv" = "SaGv_Enabled"
- # This disabled autonomous GPIO power management, otherwise
- # old cr50 FW only supports short pulses; need to clarify
- # the minimum PCH IRQ pulse width with Intel, b/180111628
- register "gpio_override_pm" = "1"
- register "gpio_pm[COMM_0]" = "0"
- register "gpio_pm[COMM_1]" = "0"
- register "gpio_pm[COMM_2]" = "0"
- register "gpio_pm[COMM_3]" = "0"
- register "gpio_pm[COMM_4]" = "0"
- register "gpio_pm[COMM_5]" = "0"
-
# FIVR configurations for kano are disabled since the board doesn't have V1p05 and Vnn
# bypass rails implemented.
register "ext_fivr_settings" = "{