Beginning with Family 17h products (a.k.a. “Zen” cores), AMD changed their paradigm for initializing the system and this requires major modifications to the execution flow of coreboot. This file discusses the new boot flow, and challenges, and the tradeoffs of the initial port into coreboot.
Family 17h products are x86-based designs. This documentation assumes familiarity with x86, its reset state and its early initialization requirements.
To the extent necessary, the role of the AMD Secure Processor (a.k.a. Platform Security Processor or PSP) in system initialization is addressed here. The PSP specification1 is available only with an NDA. coreboot relies on util/amdfwtool to build the structures and add various other firmware to the final image2. The Family 17h PSP design guide adds a new BIOS Directory Table, similar to the PSP Directory Table.
Support in coreboot for modern AMD products is based on AMD’s reference code: AMD Generic Encapsulated Software Architecture (AGESATM). AGESA contains the technology for enabling DRAM, configuring proprietary core logic, assistance with generating ACPI tables, and other features.
AGESA for products earlier than Family 17h is known as v5 or Arch20083. Also note that coreboot currently contains both open source AGESA and closed source implementations (binaryPI) compiled from AGESA.
The first AMD Family 17h device ported to coreboot is codenamed “Picasso”4, and will be added to soc/amd/picasso.
AMD has ported early AGESA features to the PSP, which now discovers, enables and trains DRAM. Unlike any other x86 device in coreboot, a Picasso system has DRAM online prior to the first instruction fetch.
Cache-as-RAM (CAR) is no longer a supportable feature in AMD hardware. Early code expecting CAR behavior must account for writes escaping the L2 cache and going to DRAM.
Without any practical need for CAR, or DRAM initialization, coreboot should arguably skip bootblock and romstage, and possibly use ramstage as the BIOS image. This approach presents a number of challenges:
AGESA supporting Picasso is now at v9. Unlike Arch2008, which defines granular entry points for easy inclusion to a legacy BIOS, v9 is rewritten for compilation into a UEFI. The source follows UEFI standards, i.e. assumes the presence of UEFI phases, implements dependency expressions, much functionality is rewritten as libraries, etc. It would, in no way, fit into the v5 model used in coreboot.
The following steps occur prior to x86 processor operation.
As mentioned above, prior to releasing the x86 main core from reset, the PSP decompresses a BIOS image into DRAM. The PSP uses a specific BIOS Directory Table entry type to determine the source address (in flash), the destination address (in DRAM), and the destination size. The decompressed image is at the top of the destination region. The PSP then
Calculates the x86 reset vector as
reset_vector = dest_addr + dest_size - 0x10
Sets x86 CS descriptor shadow register to
base = dest_addr + dest_size - 0x10000 limit = 0xffff
Like all x86 devices, the main core is allowed to begin executing instructions with
CS:IP = 0xf000:0xfff0
For example, assume the BIOS Directory Table indicates
destination = 0x9b00000 size = 0x300000
… then the BIOS image is placed at the topmost position the region 0x9b00000-0x9dfffff and
reset_vector = 0x9dffff0 CS_shdw_base = 0x9df0000 CS:IP = 0xf000:0xfff0
Although the x86 behaves as though it began executing at 0xfffffff0 i.e. 0xf000:0xfff0, the initial GDT load must use the physical address of the table and not the typical CS-centric address. And, the first jump to protected mode must jump to the physical address in DRAM. Any code that is position-dependent must be linked to run at the final destination.
Supporting Picasso doesn’t fit perfectly with many of the coreboot assumptions about x86 processors. Changes are introduced primarily into arch/x86 to accommodate a processor starting in DRAM and at a nontraditional reset vector.
The traditional coreboot bootblock and romstage rely on cache-as-RAM and a linker script that positions temporary storage accordingly. A substitute for the DCACHE variables, called EARLYRAM, is introduced. Like DCACHE, this allows for a consistent mapping of early regions required across multiple stages prior to cbmem coming online. Examples are the _preram_cbmem_console and _timestamp.
Due to Picasso's unique nature of starting with DRAM already available, no early stages run as execute-in-place (XIP). All post-bootblock stages are copied from the BIOS flash into DRAM for faster performance, and these regions are marked reserved later in POST.
Unlike CAR-based systems, and because Picasso does not run early stages as XIP, its early stages are not constrained in their use of .bss or .data sections. All stages' .bss is zeroed, and all .data sections are fully R/W at load time.
Picasso uses a bootblock that mirrors a traditional bootblock as much as possible. Because the image is loaded by the PSP, the bootblock is not restricted to the top of the BIOS flash device. The compressed image is added into the PSP's amdfw.rom
build.
Development is currently underway for the vboot app, and potentially an x86-based verstage companion. This document shall be updated once the design is finalized and functioning. Support for the PSP honoring the presence of the vboot app is available only in certain SKUs.
A traditional romstage is maintained for Picasso. The primary reason for this choice is to remain compatible with coreboot conventions and to support the FSP 2.0 driver. Picasso's romstage uses an fsp_memory_init() call to glean the memory map from AGESA. (See below.) fsp_memory_init() brings cbmem online before returning to the caller.
No postcar stage is required or supported.
Due to the current restriction on publishing AGESA source, a pre-built binary solution remains a requirement. Modifying v9 to conform to the existing v5 binaryPI interface was considered impractical.
Given the UEFI nature of modern AGESA, and the existing open source work from Intel, Picasso shall support AGESA via an FSP-like prebuilt image. The Intel Firmware Support Package5 combines reference code with EDK II source to create a modular image with discoverable entry points. coreboot source already contains knowledge of FSP, how to parse it, integrate it, and how to communicate with it. Picasso's FSP is compatible with rev. 2.0 of the External Architecture Specification. Deviations, e.g., no FSP-T support, shall be published in an Integration Guide.