ACPI: Obsolete FADT p_lvl2_lat and p_lvl3_lat fields
After the obsoletion of Processor() it is necessary to provide
_CST package to define P_LVLx IO addresses for C2/C3 transitions.
The latency values from _CST will always replace those in FADT.
Change-Id: I3230be719659fe9cdf9ed6ae73bc91b05093ab97
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c
index 492d043..f8994eb 100644
--- a/src/acpi/acpi.c
+++ b/src/acpi/acpi.c
@@ -1685,6 +1685,10 @@
/* should be 0 ACPI 3.0 */
fadt->reserved = 0;
+ /* P_LVLx latencies are not used as CPU _CST will override them. */
+ fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
+ fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
+
fadt->preferred_pm_profile = acpi_get_preferred_pm_profile();
if (CONFIG(USE_PC_CMOS_ALTCENTURY))
diff --git a/src/soc/amd/cezanne/acpi.c b/src/soc/amd/cezanne/acpi.c
index 08effca..0d2c517 100644
--- a/src/soc/amd/cezanne/acpi.c
+++ b/src/soc/amd/cezanne/acpi.c
@@ -69,10 +69,6 @@
fill_fadt_extended_pm_regs(fadt);
- /* p_lvl2_lat and p_lvl3_lat match what the AGESA code does, but those values are
- overridden by the _CST packages in the processor devices. */
- fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
- fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
fadt->day_alrm = RTC_DATE_ALARM;
fadt->century = RTC_ALT_CENTURY;
fadt->iapc_boot_arch = cfg->common_config.fadt_boot_arch; /* legacy free default */
diff --git a/src/soc/amd/glinda/acpi.c b/src/soc/amd/glinda/acpi.c
index cb8039d..2943d7d 100644
--- a/src/soc/amd/glinda/acpi.c
+++ b/src/soc/amd/glinda/acpi.c
@@ -72,10 +72,6 @@
fill_fadt_extended_pm_regs(fadt);
- /* p_lvl2_lat and p_lvl3_lat match what the AGESA code does, but those values are
- overridden by the _CST packages in the processor devices. */
- fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
- fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
fadt->day_alrm = RTC_DATE_ALARM;
fadt->century = RTC_ALT_CENTURY;
fadt->iapc_boot_arch = cfg->common_config.fadt_boot_arch; /* legacy free default */
diff --git a/src/soc/amd/mendocino/acpi.c b/src/soc/amd/mendocino/acpi.c
index 17d8955..8fb7237 100644
--- a/src/soc/amd/mendocino/acpi.c
+++ b/src/soc/amd/mendocino/acpi.c
@@ -71,10 +71,6 @@
fill_fadt_extended_pm_regs(fadt);
- /* p_lvl2_lat and p_lvl3_lat match what the AGESA code does, but those values are
- overridden by the _CST packages in the processor devices. */
- fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
- fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
fadt->day_alrm = RTC_DATE_ALARM;
fadt->century = RTC_ALT_CENTURY;
fadt->iapc_boot_arch = cfg->common_config.fadt_boot_arch; /* legacy free default */
diff --git a/src/soc/amd/phoenix/acpi.c b/src/soc/amd/phoenix/acpi.c
index 5e37a27..ea2a997 100644
--- a/src/soc/amd/phoenix/acpi.c
+++ b/src/soc/amd/phoenix/acpi.c
@@ -72,10 +72,6 @@
fill_fadt_extended_pm_regs(fadt);
- /* p_lvl2_lat and p_lvl3_lat match what the AGESA code does, but those values are
- overridden by the _CST packages in the processor devices. */
- fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
- fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
fadt->day_alrm = RTC_DATE_ALARM;
fadt->century = RTC_ALT_CENTURY;
fadt->iapc_boot_arch = cfg->common_config.fadt_boot_arch; /* legacy free default */
diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c
index 227a5d8..1a824a7 100644
--- a/src/soc/amd/picasso/acpi.c
+++ b/src/soc/amd/picasso/acpi.c
@@ -77,10 +77,6 @@
fill_fadt_extended_pm_regs(fadt);
- /* p_lvl2_lat and p_lvl3_lat match what the AGESA code does, but those values are
- overridden by the _CST packages in the processor devices. */
- fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
- fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
fadt->day_alrm = RTC_DATE_ALARM;
fadt->iapc_boot_arch = cfg->fadt_boot_arch; /* legacy free default */
fadt->flags |= ACPI_FADT_WBINVD | /* See table 5-34 ACPI 6.3 spec */
diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c
index 947c806..d6dec6f 100644
--- a/src/soc/amd/stoneyridge/acpi.c
+++ b/src/soc/amd/stoneyridge/acpi.c
@@ -71,10 +71,6 @@
fill_fadt_extended_pm_regs(fadt);
- /* p_lvl2_lat and p_lvl3_lat match what the AGESA code does, but those values are
- overridden by the _CST packages in the PSTATE SSDT. */
- fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
- fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
fadt->duty_offset = 1; /* CLK_VAL bits 3:1 */
fadt->duty_width = 3; /* CLK_VAL bits 3:1 */
fadt->day_alrm = RTC_DATE_ALARM;
diff --git a/src/soc/intel/xeon_sp/spr/soc_acpi.c b/src/soc/intel/xeon_sp/spr/soc_acpi.c
index c609f4f..0233c37 100644
--- a/src/soc/intel/xeon_sp/spr/soc_acpi.c
+++ b/src/soc/intel/xeon_sp/spr/soc_acpi.c
@@ -48,8 +48,6 @@
fadt->pm2_cnt_blk = pmbase + PM2_CNT;
fadt->pm2_cnt_len = 1;
fadt->gpe0_blk = pmbase + 0x60;
- fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
- fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
fadt->duty_offset = 1;
fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
diff --git a/src/southbridge/amd/pi/hudson/fadt.c b/src/southbridge/amd/pi/hudson/fadt.c
index 4989d6b..fe286fe 100644
--- a/src/southbridge/amd/pi/hudson/fadt.c
+++ b/src/southbridge/amd/pi/hudson/fadt.c
@@ -44,8 +44,6 @@
fadt->pm_tmr_len = 4; /* 32 bits */
fadt->gpe0_blk_len = 8; /* 64 bits */
- fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
- fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
fadt->duty_offset = 1; /* CLK_VAL bits 3:1 */
fadt->duty_width = 3; /* CLK_VAL bits 3:1 */
fadt->day_alrm = 0; /* 0x7d these have to be */
diff --git a/src/southbridge/intel/bd82x6x/fadt.c b/src/southbridge/intel/bd82x6x/fadt.c
index be315af..a9e7a36 100644
--- a/src/southbridge/intel/bd82x6x/fadt.c
+++ b/src/southbridge/intel/bd82x6x/fadt.c
@@ -31,9 +31,6 @@
fadt->pm2_cnt_len = 1;
fadt->pm_tmr_len = 4;
fadt->gpe0_blk_len = 16;
- /* P_LVLx not used */
- fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
- fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
/* P_CNT not supported */
fadt->duty_offset = 0;
fadt->duty_width = 0;
diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c
index fc3258a..681d09c 100644
--- a/src/southbridge/intel/i82371eb/fadt.c
+++ b/src/southbridge/intel/i82371eb/fadt.c
@@ -36,8 +36,6 @@
fadt->pm_tmr_len = 4;
fadt->gpe0_blk_len = 4;
- fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
- fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
fadt->duty_offset = 1; /* bit 1:3 in PCNTRL reg (pmbase+0x10) */
fadt->duty_width = 3; /* this width is in bits */
fadt->day_alrm = 0x0d; /* rtc CMOS RAM offset */
diff --git a/src/southbridge/intel/ibexpeak/fadt.c b/src/southbridge/intel/ibexpeak/fadt.c
index 9921b4d..d6084ee 100644
--- a/src/southbridge/intel/ibexpeak/fadt.c
+++ b/src/southbridge/intel/ibexpeak/fadt.c
@@ -31,9 +31,6 @@
fadt->pm2_cnt_len = 1;
fadt->pm_tmr_len = 4;
fadt->gpe0_blk_len = 16;
- /* P_LVLx not used */
- fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
- fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
/* P_CNT not supported */
fadt->duty_offset = 0;
fadt->duty_width = 0;
diff --git a/src/southbridge/intel/lynxpoint/fadt.c b/src/southbridge/intel/lynxpoint/fadt.c
index fc08f01..ba9439c 100644
--- a/src/southbridge/intel/lynxpoint/fadt.c
+++ b/src/southbridge/intel/lynxpoint/fadt.c
@@ -44,9 +44,6 @@
else
fadt->gpe0_blk_len = 2 * 8;
- /* P_LVLx not used */
- fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
- fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
fadt->duty_offset = 0;
fadt->duty_width = 0;
fadt->day_alrm = 0xd;