nb/intel/ironlake: Add SAD DRAM register definitions
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change.
Change-Id: I66b87d15f6b741c6fc935106c35b201fbd9ab2c6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h
index afd3082..fa59565 100644
--- a/src/northbridge/intel/ironlake/ironlake.h
+++ b/src/northbridge/intel/ironlake/ironlake.h
@@ -57,6 +57,9 @@
#define SAD_PCIEXBAR 0x50
+#define SAD_DRAM_RULE(x) (0x80 + 4 * (x)) /* 0-7 */
+#define SAD_INTERLEAVE_LIST(x) (0xc0 + 4 * (x)) /* 0-7 */
+
/* Device 0:2.0 PCI configuration space (Graphics Device) */
diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c
index ecfbd8a..f8f6b74 100644
--- a/src/northbridge/intel/ironlake/raminit.c
+++ b/src/northbridge/intel/ironlake/raminit.c
@@ -1337,9 +1337,9 @@
MCHBAR16_OR(0x612, 0x100);
MCHBAR16_OR(0x214, 0x3E00);
for (i = 0; i < 8; i++) {
- pci_write_config32(QPI_SAD, 0x80 + 4 * i,
+ pci_write_config32(QPI_SAD, SAD_DRAM_RULE(i),
(info->total_memory_mb - 64) | !i | 2);
- pci_write_config32(QPI_SAD, 0xc0 + 4 * i, 0);
+ pci_write_config32(QPI_SAD, SAD_INTERLEAVE_LIST(i), 0);
}
}
@@ -1452,10 +1452,10 @@
memory_map[1] = 4096;
for (i = 0; i < ARRAY_SIZE(memory_map); i++) {
current_limit = MAX(current_limit, memory_map[i] & ~1);
- pci_write_config32(QPI_SAD, 4 * i + 0x80,
+ pci_write_config32(QPI_SAD, SAD_DRAM_RULE(i),
(memory_map[i] & 1) | ALIGN_DOWN(current_limit -
1, 64) | 2);
- pci_write_config32(QPI_SAD, 4 * i + 0xc0, 0);
+ pci_write_config32(QPI_SAD, SAD_INTERLEAVE_LIST(i), 0);
}
}