diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h
index a3b4faa..46ebfc3 100644
--- a/src/northbridge/intel/sandybridge/sandybridge.h
+++ b/src/northbridge/intel/sandybridge/sandybridge.h
@@ -40,7 +40,8 @@
 #define IVB_STEP_D0	(BASE_REV_IVB + 6)
 
 /* Intel Enhanced Debug region must be 4MB */
-#define IED_SIZE	0x400000
+
+#define IED_SIZE	CONFIG_IED_REGION_SIZE
 
 /* Northbridge BARs */
 #define DEFAULT_PCIEXBAR	CONFIG_MMCONF_BASE_ADDRESS	/* 4 KB per PCIe device */