- Moved 2 of the test cases into tests for failure
- Reworked the transformation into ssa form and now I catch all unitialized
variable uses.
- Several more test cases
- Bumped the version to 0.34
- Verified that -O2 the scc_transform now works.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@934 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
diff --git a/util/romcc/tests/simple_test56.c b/util/romcc/tests/simple_test56.c
new file mode 100644
index 0000000..831ee9a
--- /dev/null
+++ b/util/romcc/tests/simple_test56.c
@@ -0,0 +1,43 @@
+
+static void spd_enable_refresh(void)
+{
+ /*
+ * Effects: Uses serial presence detect to set the
+ * refresh rate in the DRAMC register.
+ * see spd_set_dramc for the other values.
+ * FIXME: Check for illegal/unsupported ram configurations and abort
+ */
+ static const unsigned char refresh_rates[] = {
+ 0x01, /* Normal 15.625 us -> 15.6 us */
+ 0x05, /* Reduced(.25X) 3.9 us -> 7.8 us */
+ 0x05, /* Reduced(.5X) 7.8 us -> 7.8 us */
+ 0x02, /* Extended(2x) 31.3 us -> 31.2 us */
+ 0x03, /* Extended(4x) 62.5 us -> 62.4 us */
+ 0x04, /* Extended(8x) 125 us -> 124.8 us */
+ };
+ /* Find the first dimm and assume the rest are the same */
+ int byte;
+ unsigned device;
+ unsigned refresh_rate;
+ byte = -1;
+ device = 0x50;
+ while ((byte < 0) && (device <= 0x57)) {
+ byte = __builtin_inl(device);
+ device += 1;
+ }
+ if (byte < 0) {
+ /* We couldn't find anything we must have no memory */
+ while(1);
+ }
+ byte &= 0x7f;
+ /* Default refresh rate be conservative */
+ refresh_rate = 5;
+ /* see if the ram refresh is a supported one */
+ if (byte < 6) {
+ refresh_rate = refresh_rates[byte];
+ }
+ byte = __builtin_inb(0x57);
+ byte &= 0xf8;
+ byte |= refresh_rate;
+ __builtin_outb(byte, 0x57);
+}