soc/intel/apollolake: Use CPU common library code
This patch makes SOC files to use common/block/cpu/cpulib.c
file's helper functions.
Change-Id: I529c67cf20253cf819d1c13849300788104b083c
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/19827
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index a923057..b80941d 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -55,6 +55,7 @@
select SOC_INTEL_COMMON_ACPI
select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
select SOC_INTEL_COMMON_BLOCK
+ select SOC_INTEL_COMMON_BLOCK_CPU
select SOC_INTEL_COMMON_BLOCK_FAST_SPI
select SOC_INTEL_COMMON_BLOCK_ITSS
select SOC_INTEL_COMMON_BLOCK_I2C
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index b1f92f0..6197138 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -18,7 +18,6 @@
bootblock-y += mmap_boot.c
bootblock-y += pmutil.c
bootblock-y += spi.c
-bootblock-y += tsc_freq.c
bootblock-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
bootblock-$(CONFIG_FSP_CAR) += bootblock/cache_as_ram_fsp.S
@@ -32,7 +31,6 @@
romstage-y += memmap.c
romstage-y += meminit.c
romstage-y += mmap_boot.c
-romstage-y += tsc_freq.c
romstage-y += pmutil.c
romstage-y += reset.c
romstage-y += spi.c
@@ -42,7 +40,6 @@
smm-y += gpio.c
smm-y += smihandler.c
smm-y += spi.c
-smm-y += tsc_freq.c
smm-y += uart_early.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
@@ -65,7 +62,6 @@
ramstage-y += nhlt.c
ramstage-y += systemagent.c
ramstage-y += spi.c
-ramstage-y += tsc_freq.c
ramstage-y += pmutil.c
ramstage-y += pmc.c
ramstage-y += reset.c
@@ -79,7 +75,6 @@
postcar-y += mmap_boot.c
postcar-y += spi.c
postcar-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
-postcar-y += tsc_freq.c
postcar-$(CONFIG_FSP_CAR) += exit_car_fsp.S
@@ -89,7 +84,6 @@
verstage-y += memmap.c
verstage-y += mmap_boot.c
verstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
-verstage-y += tsc_freq.c
verstage-y += pmutil.c
verstage-y += reset.c
verstage-y += spi.c
diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c
index 705567a..729134b 100644
--- a/src/soc/intel/apollolake/bootblock/bootblock.c
+++ b/src/soc/intel/apollolake/bootblock/bootblock.c
@@ -17,6 +17,7 @@
#include <arch/cpu.h>
#include <bootblock_common.h>
#include <device/pci.h>
+#include <intelblocks/cpulib.h>
#include <intelblocks/fast_spi.h>
#include <intelblocks/pcr.h>
#include <intelblocks/rtc.h>
diff --git a/src/soc/intel/apollolake/car.c b/src/soc/intel/apollolake/car.c
index 2d2f7a0..f46e0f8 100644
--- a/src/soc/intel/apollolake/car.c
+++ b/src/soc/intel/apollolake/car.c
@@ -17,8 +17,9 @@
#include <arch/cpu.h>
#include <assert.h>
+#include <cpu/x86/msr.h>
+#include <intelblocks/msr.h>
#include <program_loading.h>
-#include <soc/cpu.h>
/*
* This file supports the necessary hoops one needs to jump through since
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index e7c4d4c..ef29a03 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -22,16 +22,18 @@
#include <console/console.h>
#include <cpu/cpu.h>
#include <cpu/x86/mp.h>
+#include <cpu/x86/msr.h>
#include <device/device.h>
#include <device/pci.h>
#include <intelblocks/fast_spi.h>
+#include <intelblocks/msr.h>
#include <fsp/api.h>
#include <fsp/util.h>
+#include <intelblocks/cpulib.h>
#include <intelblocks/itss.h>
#include <romstage_handoff.h>
#include <soc/iomap.h>
#include <soc/itss.h>
-#include <soc/cpu.h>
#include <soc/intel/common/vbt.h>
#include <soc/nvs.h>
#include <soc/pci_devs.h>
@@ -547,7 +549,7 @@
static void drop_privilege_all(void)
{
/* Drop privilege level on all the CPUs */
- if (mp_run_on_all_cpus(&enable_untrusted_mode, 1000) < 0)
+ if (mp_run_on_all_cpus(&cpu_enable_untrusted_mode, 1000) < 0)
printk(BIOS_ERR, "failed to enable untrusted mode\n");
}
diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c
index 0919dfb..ec202e4 100644
--- a/src/soc/intel/apollolake/cpu.c
+++ b/src/soc/intel/apollolake/cpu.c
@@ -28,7 +28,9 @@
#include <device/device.h>
#include <device/pci.h>
#include <fsp/api.h>
+#include <intelblocks/cpulib.h>
#include <intelblocks/fast_spi.h>
+#include <intelblocks/msr.h>
#include <reg_script.h>
#include <romstage_handoff.h>
#include <soc/cpu.h>
@@ -58,13 +60,6 @@
REG_SCRIPT_END
};
-void enable_untrusted_mode(void)
-{
- msr_t msr = rdmsr(MSR_POWER_MISC);
- msr.lo |= ENABLE_IA_UNTRUSTED;
- wrmsr(MSR_POWER_MISC, msr);
-}
-
static void soc_core_init(device_t cpu)
{
/* Set core MSRs */
diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h
index 54fcf52..0e73d11 100644
--- a/src/soc/intel/apollolake/include/soc/cpu.h
+++ b/src/soc/intel/apollolake/include/soc/cpu.h
@@ -18,23 +18,10 @@
#ifndef _SOC_APOLLOLAKE_CPU_H_
#define _SOC_APOLLOLAKE_CPU_H_
-#include <intelblocks/msr.h>
-
-#ifndef __ASSEMBLER__
-#include <cpu/x86/msr.h>
-#include <device/device.h>
-
-void set_max_freq(void);
-void enable_untrusted_mode(void);
-#endif
-
#define CPUID_APOLLOLAKE_A0 0x506c8
#define CPUID_APOLLOLAKE_B0 0x506c9
/* Common Timer Copy (CTC) frequency - 19.2MHz. */
#define CTC_FREQ 19200000
-/* This is burst mode BIT 38 in MSR_IA32_MISC_ENABLES MSR at offset 1A0h */
-#define APL_BURST_MODE_DISABLE 0x40
-
#endif /* _SOC_APOLLOLAKE_CPU_H_ */
diff --git a/src/soc/intel/apollolake/include/soc/romstage.h b/src/soc/intel/apollolake/include/soc/romstage.h
index 6ae46b6..fe3add6 100644
--- a/src/soc/intel/apollolake/include/soc/romstage.h
+++ b/src/soc/intel/apollolake/include/soc/romstage.h
@@ -21,6 +21,7 @@
#include <arch/cpu.h>
#include <fsp/api.h>
+void set_max_freq(void);
void mainboard_memory_init_params(FSPM_UPD *mupd);
void mainboard_save_dimm_info(void);
diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c
index 3ceb066..bf89a09 100644
--- a/src/soc/intel/apollolake/pmutil.c
+++ b/src/soc/intel/apollolake/pmutil.c
@@ -25,6 +25,7 @@
#include <rules.h>
#include <device/pci_def.h>
#include <halt.h>
+#include <intelblocks/msr.h>
#include <soc/iomap.h>
#include <soc/cpu.h>
#include <soc/pci_devs.h>
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index 6d04878..79b3cfd 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -31,6 +31,7 @@
#include <fsp/api.h>
#include <fsp/memmap.h>
#include <fsp/util.h>
+#include <intelblocks/cpulib.h>
#include <intelblocks/systemagent.h>
#include <reset.h>
#include <soc/cpu.h>
@@ -188,6 +189,27 @@
return true;
}
+void set_max_freq(void)
+{
+ if (cpu_get_burst_mode_state() == BURST_MODE_UNAVAILABLE) {
+ /* Burst Mode has been factory configured as disabled
+ * and is not available in this physical processor
+ * package.
+ */
+ printk(BIOS_DEBUG, "Burst Mode is factory disabled\n");
+ return;
+ }
+
+ /* Enable burst mode */
+ cpu_enable_burst_mode();
+
+ /* Enable speed step. */
+ cpu_enable_eist();
+
+ /* Set P-State ratio */
+ cpu_set_p_state_to_turbo_ratio();
+}
+
asmlinkage void car_stage_entry(void)
{
struct postcar_frame pcf;
diff --git a/src/soc/intel/apollolake/tsc_freq.c b/src/soc/intel/apollolake/tsc_freq.c
deleted file mode 100644
index 18d28d8..0000000
--- a/src/soc/intel/apollolake/tsc_freq.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <cpu/intel/speedstep.h>
-#include <cpu/intel/turbo.h>
-#include <cpu/x86/msr.h>
-#include <cpu/x86/tsc.h>
-#include <soc/cpu.h>
-#include <console/console.h>
-#include <delay.h>
-#include "chip.h"
-
-void set_max_freq(void)
-{
- msr_t msr, msr_rd;
- unsigned int eax;
-
- eax = cpuid_eax(CPUID_LEAF_PM);
-
- msr = rdmsr(MSR_IA32_MISC_ENABLES);
- eax &= 0x2;
- if ((!eax) && ((msr.hi & APL_BURST_MODE_DISABLE) == 0)) {
- /* Burst Mode has been factory configured as disabled
- * and is not available in this physical processor
- * package.
- */
- printk(BIOS_DEBUG, "Burst Mode is factory disabled\n");
- return;
- }
-
- /* Enable burst mode */
- msr.hi &= ~APL_BURST_MODE_DISABLE;
- wrmsr(MSR_IA32_MISC_ENABLES, msr);
-
- /* Enable speed step. */
- msr = rdmsr(MSR_IA32_MISC_ENABLES);
- msr.lo |= 1 << 16;
- wrmsr(MSR_IA32_MISC_ENABLES, msr);
-
- /* Set P-State ratio */
- msr = rdmsr(IA32_PERF_CTL);
- msr.lo &= ~0xff00;
-
- /* Read the frequency limit ratio and set it properly in PERF_CTL */
- msr_rd = rdmsr(FREQ_LIMIT_RATIO);
- msr.lo |= (msr_rd.lo & 0xff) << 8;
-
- wrmsr(IA32_PERF_CTL, msr);
-}