nb/intel/sandybridge: Use new fixed BAR accessors
One instance in northbridge.c breaks reproduciblity when changed.
Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 remains identical.
Change-Id: I2148183827bcacc9e6edb91b26ad35eb2dae5090
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51866
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/northbridge/intel/sandybridge/raminit_iosav.c b/src/northbridge/intel/sandybridge/raminit_iosav.c
index b9533baf..e337c40 100644
--- a/src/northbridge/intel/sandybridge/raminit_iosav.c
+++ b/src/northbridge/intel/sandybridge/raminit_iosav.c
@@ -17,10 +17,10 @@
void iosav_write_sequence(const int ch, const struct iosav_ssq *seq, const unsigned int length)
{
for (unsigned int i = 0; i < length; i++) {
- MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(ch, i)) = seq[i].sp_cmd_ctrl.raw;
- MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(ch, i)) = seq[i].subseq_ctrl.raw;
- MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(ch, i)) = seq[i].sp_cmd_addr.raw;
- MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(ch, i)) = seq[i].addr_update.raw;
+ mchbar_write32(IOSAV_n_SP_CMD_CTRL_ch(ch, i), seq[i].sp_cmd_ctrl.raw);
+ mchbar_write32(IOSAV_n_SUBSEQ_CTRL_ch(ch, i), seq[i].subseq_ctrl.raw);
+ mchbar_write32(IOSAV_n_SP_CMD_ADDR_ch(ch, i), seq[i].sp_cmd_addr.raw);
+ mchbar_write32(IOSAV_n_ADDR_UPDATE_ch(ch, i), seq[i].addr_update.raw);
}
ssq_count = length;
@@ -32,13 +32,13 @@
if (ssq_count == 0)
return;
- MCHBAR32(IOSAV_SEQ_CTL_ch(ch)) = loops | ((ssq_count - 1) << 18) | (as_timer << 22);
+ mchbar_write32(IOSAV_SEQ_CTL_ch(ch), loops | (ssq_count - 1) << 18 | as_timer << 22);
}
void wait_for_iosav(int channel)
{
while (1) {
- if (MCHBAR32(IOSAV_STATUS_ch(channel)) & 0x50)
+ if (mchbar_read32(IOSAV_STATUS_ch(channel)) & 0x50)
return;
}
}