nb/intel/sandybridge: Use new fixed BAR accessors
One instance in northbridge.c breaks reproduciblity when changed.
Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 remains identical.
Change-Id: I2148183827bcacc9e6edb91b26ad35eb2dae5090
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51866
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c
index 1e5458d..38adbce 100644
--- a/src/northbridge/intel/sandybridge/gma.c
+++ b/src/northbridge/intel/sandybridge/gma.c
@@ -347,7 +347,7 @@
gtt_write_powermeter(snb_pm_gt2);
}
} else {
- u32 unit = MCHBAR32(0x5938) & 0xf;
+ u32 unit = mchbar_read32(0x5938) & 0xf;
if (reg32 & (1 << 13)) {
/* GT1 SKU */
@@ -355,7 +355,7 @@
gtt_write_powermeter(ivb_pm_gt1);
} else {
/* GT2 SKU */
- u32 tdp = MCHBAR32(0x5930) & 0x7fff;
+ u32 tdp = mchbar_read32(0x5930) & 0x7fff;
tdp /= (1 << unit);
if (tdp <= 17) {
@@ -467,7 +467,7 @@
/* 12: Normal Frequency Request */
/* RPNFREQ_VAL comes from MCHBAR 0x5998 23:16 */
/* only the lower 7 bits are used and shifted left by 25 */
- reg32 = MCHBAR32(0x5998);
+ reg32 = mchbar_read32(0x5998);
reg32 >>= 16;
reg32 &= 0x7f;
reg32 <<= 25;