northbridge: Drop print_ implementation from non-romcc boards
Because we had no stack on romcc boards, we had a separate, not as
powerful clone of printk: print_*. Back in the day, like more than
half a decade ago, we migrated a lot of boards to printk, but we never
cleaned up the existing code to be consistent. instead, we worked around
the problem with a very messy console.h (nowadays the mess is hidden in
romstage_console.c and early_print.h)
This patch cleans up the northbridge code to use printk() on all non-ROMCC
boards.
Change-Id: I4a36cd965c58aae65d74ce1e697dc0d0f58f47a1
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/7856
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
diff --git a/src/northbridge/intel/e7501/debug.c b/src/northbridge/intel/e7501/debug.c
index 07f1596..32a1428 100644
--- a/src/northbridge/intel/e7501/debug.c
+++ b/src/northbridge/intel/e7501/debug.c
@@ -5,12 +5,8 @@
#if 1
static void print_debug_pci_dev(unsigned dev)
{
- print_debug("PCI: ");
- print_debug_hex8((dev >> 16) & 0xff);
- print_debug_char(':');
- print_debug_hex8((dev >> 11) & 0x1f);
- print_debug_char('.');
- print_debug_hex8((dev >> 8) & 7);
+ printk(BIOS_DEBUG, "PCI: %02x:%02x.%x",
+ (dev >> 16) & 0xff, (dev >> 11) & 0x1f, (dev >> 8) & 7);
}
static inline void print_pci_devices(void)
@@ -27,7 +23,7 @@
continue;
}
print_debug_pci_dev(dev);
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
}
@@ -38,24 +34,12 @@
for(i = 0; i < 256; i++) {
unsigned char val;
- if ((i & 0x0f) == 0) {
-#if !defined(__ROMCC__)
+ if ((i & 0x0f) == 0)
printk(BIOS_DEBUG, "\n%02x:",i);
-#else
- print_debug("\n");
- print_debug_hex8(i);
- print_debug_char(':');
-#endif
- }
val = pci_read_config8(dev, i);
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, " %02x", val);
-#else
- print_debug_char(' ');
- print_debug_hex8(val);
-#endif
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
static inline void dump_pci_devices(void)
@@ -95,98 +79,55 @@
static inline void dump_spd_registers(const struct mem_controller *ctrl)
{
int i;
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
for(i = 0; i < 4; i++) {
unsigned device;
device = ctrl->channel0[i];
if (device) {
int j;
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, "dimm: %02x.0: %02x", i, device);
-#else
- print_debug("dimm: ");
- print_debug_hex8(i);
- print_debug(".0: ");
- print_debug_hex8(device);
-#endif
for(j = 0; j < 128; j++) {
int status;
unsigned char byte;
- if ((j & 0xf) == 0) {
-#if !defined(__ROMCC__)
+ if ((j & 0xf) == 0)
printk(BIOS_DEBUG, "\n%02x: ", j);
-#else
- print_debug("\n");
- print_debug_hex8(j);
- print_debug(": ");
-#endif
- }
status = smbus_read_byte(device, j);
if (status < 0) {
break;
}
byte = status & 0xff;
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, "%02x ", byte);
-#else
- print_debug_hex8(byte);
- print_debug_char(' ');
-#endif
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
device = ctrl->channel1[i];
if (device) {
int j;
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, "dimm: %02x.1: %02x", i, device);
-#else
- print_debug("dimm: ");
- print_debug_hex8(i);
- print_debug(".1: ");
- print_debug_hex8(device);
-#endif
for(j = 0; j < 128; j++) {
int status;
unsigned char byte;
- if ((j & 0xf) == 0) {
-#if !defined(__ROMCC__)
+ if ((j & 0xf) == 0)
printk(BIOS_DEBUG, "\n%02x: ", j);
-#else
- print_debug("\n");
- print_debug_hex8(j);
- print_debug(": ");
-#endif
- }
status = smbus_read_byte(device, j);
if (status < 0) {
break;
}
byte = status & 0xff;
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, "%02x ", byte);
-#else
- print_debug_hex8(byte);
- print_debug_char(' ');
-#endif
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
}
}
static inline void dump_smbus_registers(void)
{
unsigned device;
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
for(device = 1; device < 0x80; device++) {
int j;
if( smbus_read_byte(device, 0) < 0 ) continue;
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, "smbus: %02x", device);
-#else
- print_debug("smbus: ");
- print_debug_hex8(device);
-#endif
for(j = 0; j < 256; j++) {
int status;
unsigned char byte;
@@ -194,24 +135,12 @@
if (status < 0) {
break;
}
- if ((j & 0xf) == 0) {
-#if !defined(__ROMCC__)
+ if ((j & 0xf) == 0)
printk(BIOS_DEBUG, "\n%02x: ",j);
-#else
- print_debug("\n");
- print_debug_hex8(j);
- print_debug(": ");
-#endif
- }
byte = status & 0xff;
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, "%02x ", byte);
-#else
- print_debug_hex8(byte);
- print_debug_char(' ');
-#endif
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
}
@@ -219,31 +148,15 @@
{
int i;
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, "%04x:\n", port);
-#else
- print_debug_hex16(port);
- print_debug(":\n");
-#endif
for(i=0;i<256;i++) {
uint8_t val;
- if ((i & 0x0f) == 0) {
-#if !defined(__ROMCC__)
+ if ((i & 0x0f) == 0)
printk(BIOS_DEBUG, "%02x:", i);
-#else
- print_debug_hex8(i);
- print_debug_char(':');
-#endif
- }
val = inb(port);
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, " %02x",val);
-#else
- print_debug_char(' ');
- print_debug_hex8(val);
-#endif
if ((i & 0x0f) == 0x0f) {
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
port++;
}
@@ -252,24 +165,12 @@
static inline void dump_mem(unsigned start, unsigned end)
{
unsigned i;
- print_debug("dump_mem:");
+ printk(BIOS_DEBUG, "dump_mem:");
for(i=start;i<end;i++) {
- if((i & 0xf)==0) {
-#if !defined(__ROMCC__)
+ if((i & 0xf)==0)
printk(BIOS_DEBUG, "\n%08x:", i);
-#else
- print_debug("\n");
- print_debug_hex32(i);
- print_debug(":");
-#endif
- }
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i));
-#else
- print_debug(" ");
- print_debug_hex8((unsigned char)*((unsigned char *)i));
-#endif
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
#endif
diff --git a/src/northbridge/intel/e7501/raminit.c b/src/northbridge/intel/e7501/raminit.c
index 2247a25..22d1bbc 100644
--- a/src/northbridge/intel/e7501/raminit.c
+++ b/src/northbridge/intel/e7501/raminit.c
@@ -27,9 +27,9 @@
//#define VALIDATE_DIMM_COMPATIBILITY
#if CONFIG_DEBUG_RAM_SETUP
-#define RAM_DEBUG_MESSAGE(x) print_debug(x)
-#define RAM_DEBUG_HEX32(x) print_debug_hex32(x)
-#define RAM_DEBUG_HEX8(x) print_debug_hex8(x)
+#define RAM_DEBUG_MESSAGE(x) printk(BIOS_DEBUG, x)
+#define RAM_DEBUG_HEX32(x) printk(BIOS_DEBUG, "%08x", x)
+#define RAM_DEBUG_HEX8(x) printk(BIOS_DEBUG, "%02x", x)
#define DUMPNORTH() dump_pci_device(PCI_DEV(0, 0, 0))
#else
#define RAM_DEBUG_MESSAGE(x)
@@ -784,7 +784,7 @@
spd_read_byte(channel1_dimm, SPD_MODULE_ATTRIBUTES);
if (!(spd_value & MODULE_REGISTERED) || (spd_value < 0)) {
- print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\n");
+ printk(BIOS_DEBUG, "Skipping un-matched DIMMs - only dual-channel operation supported\n");
continue;
}
#ifdef VALIDATE_DIMM_COMPATIBILITY
@@ -812,11 +812,11 @@
// Made it through all the checks, this DIMM pair is usable
dimm_mask |= ((1 << i) | (1 << (MAX_DIMM_SOCKETS_PER_CHANNEL + i)));
} else
- print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\n");
+ printk(BIOS_DEBUG, "Skipping un-matched DIMMs - only dual-channel operation supported\n");
#else
switch (bDualChannel) {
case 0:
- print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\n");
+ printk(BIOS_DEBUG, "Skipping un-matched DIMMs - only dual-channel operation supported\n");
break;
default:
@@ -1523,13 +1523,13 @@
die_on_spd_error(value);
value &= 0x7f; // Mask off self-refresh bit
if (value > MAX_SPD_REFRESH_RATE) {
- print_err("unsupported refresh rate\n");
+ printk(BIOS_ERR, "unsupported refresh rate\n");
continue;
}
// Get the appropriate E7501 refresh mode for this DIMM
dimm_refresh_mode = refresh_rate_map[value];
if (dimm_refresh_mode > 7) {
- print_err("unsupported refresh rate\n");
+ printk(BIOS_ERR, "unsupported refresh rate\n");
continue;
}
// If this DIMM requires more frequent refresh than others,
@@ -1961,7 +1961,7 @@
dimm_mask = spd_get_supported_dimms(ctrl);
if (dimm_mask == 0) {
- print_debug("No usable memory for this controller\n");
+ printk(BIOS_DEBUG, "No usable memory for this controller\n");
} else {
enable_e7501_clocks(dimm_mask);
diff --git a/src/northbridge/intel/e7505/debug.c b/src/northbridge/intel/e7505/debug.c
index 3d6ca2a..cdf6e7e 100644
--- a/src/northbridge/intel/e7505/debug.c
+++ b/src/northbridge/intel/e7505/debug.c
@@ -15,12 +15,8 @@
void print_debug_pci_dev(unsigned dev)
{
- print_debug("PCI: ");
- print_debug_hex8((dev >> 16) & 0xff);
- print_debug_char(':');
- print_debug_hex8((dev >> 11) & 0x1f);
- print_debug_char('.');
- print_debug_hex8((dev >> 8) & 7);
+ printk(BIOS_DEBUG, "PCI: %02x:%02x.%x",
+ (dev >> 16) & 0xff, (dev >> 11) & 0x1f, (dev >> 8) & 7);
}
void print_pci_devices(void)
@@ -37,7 +33,7 @@
continue;
}
print_debug_pci_dev(dev);
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
}
@@ -48,24 +44,12 @@
for(i = 0; i < 256; i++) {
unsigned char val;
- if ((i & 0x0f) == 0) {
-#if !defined(__ROMCC__)
+ if ((i & 0x0f) == 0)
printk(BIOS_DEBUG, "\n%02x:",i);
-#else
- print_debug("\n");
- print_debug_hex8(i);
- print_debug_char(':');
-#endif
- }
val = pci_read_config8(dev, i);
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, " %02x", val);
-#else
- print_debug_char(' ');
- print_debug_hex8(val);
-#endif
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
void dump_pci_devices(void)
@@ -105,98 +89,55 @@
void dump_spd_registers(const struct mem_controller *ctrl)
{
int i;
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
for(i = 0; i < 4; i++) {
unsigned device;
device = ctrl->channel0[i];
if (device) {
int j;
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, "dimm: %02x.0: %02x", i, device);
-#else
- print_debug("dimm: ");
- print_debug_hex8(i);
- print_debug(".0: ");
- print_debug_hex8(device);
-#endif
for(j = 0; j < 128; j++) {
int status;
unsigned char byte;
- if ((j & 0xf) == 0) {
-#if !defined(__ROMCC__)
+ if ((j & 0xf) == 0)
printk(BIOS_DEBUG, "\n%02x: ", j);
-#else
- print_debug("\n");
- print_debug_hex8(j);
- print_debug(": ");
-#endif
- }
status = spd_read_byte(device, j);
if (status < 0) {
break;
}
byte = status & 0xff;
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, "%02x ", byte);
-#else
- print_debug_hex8(byte);
- print_debug_char(' ');
-#endif
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
device = ctrl->channel1[i];
if (device) {
int j;
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, "dimm: %02x.1: %02x", i, device);
-#else
- print_debug("dimm: ");
- print_debug_hex8(i);
- print_debug(".1: ");
- print_debug_hex8(device);
-#endif
for(j = 0; j < 128; j++) {
int status;
unsigned char byte;
- if ((j & 0xf) == 0) {
-#if !defined(__ROMCC__)
+ if ((j & 0xf) == 0)
printk(BIOS_DEBUG, "\n%02x: ", j);
-#else
- print_debug("\n");
- print_debug_hex8(j);
- print_debug(": ");
-#endif
- }
status = spd_read_byte(device, j);
if (status < 0) {
break;
}
byte = status & 0xff;
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, "%02x ", byte);
-#else
- print_debug_hex8(byte);
- print_debug_char(' ');
-#endif
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
}
}
void dump_smbus_registers(void)
{
unsigned device;
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
for(device = 1; device < 0x80; device++) {
int j;
if( spd_read_byte(device, 0) < 0 ) continue;
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, "smbus: %02x", device);
-#else
- print_debug("smbus: ");
- print_debug_hex8(device);
-#endif
for(j = 0; j < 256; j++) {
int status;
unsigned char byte;
@@ -204,24 +145,12 @@
if (status < 0) {
break;
}
- if ((j & 0xf) == 0) {
-#if !defined(__ROMCC__)
+ if ((j & 0xf) == 0)
printk(BIOS_DEBUG, "\n%02x: ",j);
-#else
- print_debug("\n");
- print_debug_hex8(j);
- print_debug(": ");
-#endif
- }
byte = status & 0xff;
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, "%02x ", byte);
-#else
- print_debug_hex8(byte);
- print_debug_char(' ');
-#endif
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
}
@@ -229,31 +158,15 @@
{
int i;
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, "%04x:\n", port);
-#else
- print_debug_hex16(port);
- print_debug(":\n");
-#endif
for(i=0;i<256;i++) {
uint8_t val;
- if ((i & 0x0f) == 0) {
-#if !defined(__ROMCC__)
+ if ((i & 0x0f) == 0)
printk(BIOS_DEBUG, "%02x:", i);
-#else
- print_debug_hex8(i);
- print_debug_char(':');
-#endif
- }
val = inb(port);
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, " %02x",val);
-#else
- print_debug_char(' ');
- print_debug_hex8(val);
-#endif
if ((i & 0x0f) == 0x0f) {
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
port++;
}
@@ -262,23 +175,11 @@
void dump_mem(unsigned start, unsigned end)
{
unsigned i;
- print_debug("dump_mem:");
+ printk(BIOS_DEBUG, "dump_mem:");
for(i=start;i<end;i++) {
- if((i & 0xf)==0) {
-#if !defined(__ROMCC__)
+ if((i & 0xf)==0)
printk(BIOS_DEBUG, "\n%08x:", i);
-#else
- print_debug("\n");
- print_debug_hex32(i);
- print_debug(":");
-#endif
- }
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i));
-#else
- print_debug(" ");
- print_debug_hex8((unsigned char)*((unsigned char *)i));
-#endif
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c
index 909e740..b758c61 100644
--- a/src/northbridge/intel/e7505/raminit.c
+++ b/src/northbridge/intel/e7505/raminit.c
@@ -42,9 +42,9 @@
//#define VALIDATE_DIMM_COMPATIBILITY
#if CONFIG_DEBUG_RAM_SETUP
-#define RAM_DEBUG_MESSAGE(x) print_debug(x)
-#define RAM_DEBUG_HEX32(x) print_debug_hex32(x)
-#define RAM_DEBUG_HEX8(x) print_debug_hex8(x)
+#define RAM_DEBUG_MESSAGE(x) printk(BIOS_DEBUG, x)
+#define RAM_DEBUG_HEX32(x) printk(BIOS_DEBUG, "%08x", x)
+#define RAM_DEBUG_HEX8(x) printk(BIOS_DEBUG, "%02x", x)
#define DUMPNORTH() dump_pci_device(MCHDEV)
#else
#define RAM_DEBUG_MESSAGE(x)
@@ -605,7 +605,7 @@
spd_read_byte(channel1_dimm, SPD_MODULE_ATTRIBUTES);
if (!(spd_value & MODULE_REGISTERED) || (spd_value < 0)) {
- print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\n");
+ printk(BIOS_DEBUG, "Skipping un-matched DIMMs - only dual-channel operation supported\n");
continue;
}
#ifdef VALIDATE_DIMM_COMPATIBILITY
@@ -633,11 +633,11 @@
// Made it through all the checks, this DIMM pair is usable
dimm_mask |= ((1 << i) | (1 << (MAX_DIMM_SOCKETS_PER_CHANNEL + i)));
} else
- print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\n");
+ printk(BIOS_DEBUG, "Skipping un-matched DIMMs - only dual-channel operation supported\n");
#else
switch (bDualChannel) {
case 0:
- print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\n");
+ printk(BIOS_DEBUG, "Skipping un-matched DIMMs - only dual-channel operation supported\n");
break;
default:
@@ -1379,13 +1379,13 @@
die_on_spd_error(value);
value &= 0x7f; // Mask off self-refresh bit
if (value > MAX_SPD_REFRESH_RATE) {
- print_err("unsupported refresh rate\n");
+ printk(BIOS_ERR, "unsupported refresh rate\n");
continue;
}
// Get the appropriate E7501 refresh mode for this DIMM
dimm_refresh_mode = refresh_rate_map[value];
if (dimm_refresh_mode > 7) {
- print_err("unsupported refresh rate\n");
+ printk(BIOS_ERR, "unsupported refresh rate\n");
continue;
}
// If this DIMM requires more frequent refresh than others,
@@ -1767,7 +1767,7 @@
dimm_mask = spd_get_supported_dimms(ctrl);
if (dimm_mask == 0) {
- print_debug("No usable memory for this controller\n");
+ printk(BIOS_DEBUG, "No usable memory for this controller\n");
} else {
enable_e7501_clocks(dimm_mask);
diff --git a/src/northbridge/intel/i3100/raminit.c b/src/northbridge/intel/i3100/raminit.c
index 4f5a989..ebe137b 100644
--- a/src/northbridge/intel/i3100/raminit.c
+++ b/src/northbridge/intel/i3100/raminit.c
@@ -78,7 +78,7 @@
reg |= register_values[i+2];
pci_write_config32(dev, where, reg);
}
- print_spew("done.\n");
+ printk(BIOS_SPEW, "done.\n");
}
struct dimm_size {
@@ -610,7 +610,7 @@
/* Test if we can read the spd and if ram is ddr or ddr2 */
dimm_mask = spd_detect_dimms(ctrl);
if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
- print_err("No memory for this cpu\n");
+ printk(BIOS_ERR, "No memory for this cpu\n");
return;
}
return;
@@ -686,9 +686,7 @@
die("Error - First dimm slot empty\n");
}
- print_debug("ODT Value = ");
- print_debug_hex32(data32);
- print_debug("\n");
+ printk(BIOS_DEBUG, "ODT Value = %08x\n", data32);
pci_write_config32(ctrl->f0, DDR2ODTC, data32);
@@ -916,11 +914,8 @@
}
}
- print_debug("Receive enable A = ");
- print_debug_hex32(recena);
- print_debug(", Receive enable B = ");
- print_debug_hex32(recenb);
- print_debug("\n");
+ printk(BIOS_DEBUG, "Receive enable A = %08x, Receive enable B = %08x\n",
+ recena, recenb);
/* clear out the calibration area */
write32(MCBAR+DCALDATA+(16*4), 0x00000000);
@@ -972,7 +967,7 @@
0xffffffff, 0xffffffff, 0x000000ff};
mask = spd_detect_dimms(ctrl);
- print_debug("Starting SDRAM Enable\n");
+ printk(BIOS_DEBUG, "Starting SDRAM Enable\n");
/* 0x80 */
pci_write_config32(ctrl->f0, DRM,
@@ -1013,9 +1008,7 @@
cas_latency = spd_set_drt_attributes(ctrl, mask, drc);
for(i=0;i<8;i+=2) { /* loop through each dimm to test */
- print_debug("DIMM ");
- print_debug_hex8(i);
- print_debug("\n");
+ printk(BIOS_DEBUG, "DIMM %08x\n", i);
/* Apply NOP */
do_delay();
@@ -1158,7 +1151,7 @@
write32(MCBAR+DCALCSR, 0x0008000f);
/* clear memory and init ECC */
- print_debug("Clearing memory\n");
+ printk(BIOS_DEBUG, "Clearing memory\n");
for(i=0;i<64;i+=4) {
write32(MCBAR+DCALDATA+i, 0x00000000);
}
@@ -1174,13 +1167,13 @@
data32 |= (1 << 31);
pci_write_config32(ctrl->f0, 0x98, data32);
/* wait for completion */
- print_debug("Waiting for mem complete\n");
+ printk(BIOS_DEBUG, "Waiting for mem complete\n");
while(1) {
data32 = pci_read_config32(ctrl->f0, 0x98);
if( (data32 & (1<<31)) == 0)
break;
}
- print_debug("Done\n");
+ printk(BIOS_DEBUG, "Done\n");
/* Set initialization complete */
/* 0x7c DRC */
diff --git a/src/northbridge/intel/i3100/raminit_ep80579.c b/src/northbridge/intel/i3100/raminit_ep80579.c
index cff7879..b2858e4 100644
--- a/src/northbridge/intel/i3100/raminit_ep80579.c
+++ b/src/northbridge/intel/i3100/raminit_ep80579.c
@@ -128,13 +128,7 @@
sz.side1 = 0;
sz.side2 = 0;
out:
- print_debug("dimm ");
- print_debug_hex8(device);
- print_debug(" size = ");
- print_debug_hex8(sz.side1);
- print_debug(".");
- print_debug_hex8(sz.side2);
- print_debug("\n");
+ printk(BIOS_DEBUG, "dimm %02x size = %02x.%02x\n", device, sz.side1, sz.side2);
return sz;
}
@@ -165,25 +159,19 @@
pci_write_config8(ctrl->f0, DRB+1 + (i*2), cum);
}
}
- print_debug("DRB = ");
- print_debug_hex32(pci_read_config32(ctrl->f0, DRB));
- print_debug("\n");
+ printk(BIOS_DEBUG, "DRB = %08x\n", pci_read_config32(ctrl->f0, DRB));
cum >>= 1;
/* set TOM top of memory */
pci_write_config16(ctrl->f0, TOM, cum);
- print_debug("TOM = ");
- print_debug_hex16(cum);
- print_debug("\n");
+ printk(BIOS_DEBUG, "TOM = %04x\n", cum);
/* set TOLM top of low memory */
if (cum > 0x18) {
cum = 0x18;
}
cum <<= 11;
pci_write_config16(ctrl->f0, TOLM, cum);
- print_debug("TOLM = ");
- print_debug_hex16(cum);
- print_debug("\n");
+ printk(BIOS_DEBUG, "TOLM = %04x\n", cum);
return 0;
}
@@ -198,11 +186,7 @@
device = ctrl->channel0[i];
if (device) {
byte = spd_read_byte(device, SPD_MEMORY_TYPE);
- print_debug("spd ");
- print_debug_hex8(device);
- print_debug(" = ");
- print_debug_hex8(byte);
- print_debug("\n");
+ printk(BIOS_DEBUG, "spd %02x = %02x\n", device, byte);
if (byte == 8) {
dimm_mask |= (1 << i);
}
@@ -245,11 +229,7 @@
if ((value & 0xff) == 0) die("Invalid # of banks\n");
reg += log2(value & 0xff);
- print_debug("dimm ");
- print_debug_hex8(i);
- print_debug(" reg = ");
- print_debug_hex8(reg);
- print_debug("\n");
+ printk(BIOS_DEBUG, "dimm %02x reg = %02x\n", i, reg);
/* set device density */
dra |= ((31-reg));
@@ -266,11 +246,7 @@
value = spd_read_byte(ctrl->channel0[i], SPD_NUM_DIMM_BANKS);
dra |= ((value & 0x1) << 17);
- print_debug("DRA");
- print_debug_hex8(i);
- print_debug(" = ");
- print_debug_hex32(dra);
- print_debug("\n");
+ printk(BIOS_DEBUG, "DRA%02x = %08x\n", i, dra);
pci_write_config32(ctrl->f0, DRA + (i*4), dra);
}
@@ -321,9 +297,7 @@
cl = 6;
else
die("CAS latency mismatch\n");
- print_debug("cl = ");
- print_debug_hex8(cl);
- print_debug("\n");
+ printk(BIOS_DEBUG, "cl = %02x\n", cl);
ci = cycle[index];
@@ -347,12 +321,8 @@
if (trfc < val)
trfc = val;
}
- print_debug("trc = ");
- print_debug_hex8(trc);
- print_debug("\n");
- print_debug("trfc = ");
- print_debug_hex8(trfc);
- print_debug("\n");
+ printk(BIOS_DEBUG, "trc = %02x\n", trc);
+ printk(BIOS_DEBUG, "trfc = %02x\n", trfc);
/* Tras, Trtp, Twtr in cycles */
for (i = 0; i < DIMM_SOCKETS; i++) {
@@ -372,40 +342,26 @@
if (twtr < val)
twtr = val;
}
- print_debug("tras = ");
- print_debug_hex8(tras);
- print_debug("\n");
- print_debug("trtp = ");
- print_debug_hex8(trtp);
- print_debug("\n");
- print_debug("twtr = ");
- print_debug_hex8(twtr);
- print_debug("\n");
+ printk(BIOS_DEBUG, "tras = %02x\n", tras);
+ printk(BIOS_DEBUG, "trtp = %02x\n", trtp);
+ printk(BIOS_DEBUG, "twtr = %02x\n", twtr);
val = (drt0[index] | ((trc - 11) << 12) | ((cl - 3) << 9)
| ((cl - 3) << 6) | ((cl - 3) << 3));
- print_debug("drt0 = ");
- print_debug_hex32(val);
- print_debug("\n");
+ printk(BIOS_DEBUG, "drt0 = %08x\n", val);
pci_write_config32(ctrl->f0, DRT0, val);
val = (drt1[index] | ((tras - 8) << 28) | ((trtp - 2) << 25)
| (twtr << 15));
- print_debug("drt1 = ");
- print_debug_hex32(val);
- print_debug("\n");
+ printk(BIOS_DEBUG, "drt1 = %08x\n", val);
pci_write_config32(ctrl->f0, DRT1, val);
val = (magic[index]);
- print_debug("magic = ");
- print_debug_hex32(val);
- print_debug("\n");
+ printk(BIOS_DEBUG, "magic = %08x\n", val);
pci_write_config32(PCI_DEV(0, 0x08, 0), 0xcc, val);
val = (mrs[index] | (cl << 20));
- print_debug("mrs = ");
- print_debug_hex32(val);
- print_debug("\n");
+ printk(BIOS_DEBUG, "mrs = %08x\n", val);
return val;
}
@@ -432,9 +388,7 @@
if (value > cycle)
cycle = value;
}
- print_debug("cycle = ");
- print_debug_hex8(cycle);
- print_debug("\n");
+ printk(BIOS_DEBUG, "cycle = %02x\n", cycle);
drc |= (1 << 20); /* enable ECC */
drc |= (3 << 30); /* enable CKE on each DIMM */
@@ -443,45 +397,40 @@
/* TODO check: */
/* set front side bus speed */
msr = rdmsr(MSR_FSB_FREQ); /* returns 0 on Pentium M 90nm */
- print_debug("MSR FSB_FREQ(0xcd) = ");
- print_debug_hex32(msr.hi);
- print_debug_hex32(msr.lo);
- print_debug("\n");
+ printk(BIOS_DEBUG, "MSR FSB_FREQ(0xcd) = %08x%08x\n", msr.hi, msr.lo);
/* TODO check that this msr really indicates fsb speed! */
if (msr.lo & 0x07) {
- print_info("533 MHz FSB\n");
+ printk(BIOS_INFO, "533 MHz FSB\n");
if (cycle <= 0x25) {
drc |= 0x5;
- print_info("400 MHz DDR\n");
+ printk(BIOS_INFO, "400 MHz DDR\n");
} else if (cycle <= 0x30) {
drc |= 0x7;
- print_info("333 MHz DDR\n");
+ printk(BIOS_INFO, "333 MHz DDR\n");
} else if (cycle <= 0x3d) {
drc |= 0x4;
- print_info("266 MHz DDR\n");
+ printk(BIOS_INFO, "266 MHz DDR\n");
} else {
drc |= 0x2;
- print_info("200 MHz DDR\n");
+ printk(BIOS_INFO, "200 MHz DDR\n");
}
}
else {
- print_info("400 MHz FSB\n");
+ printk(BIOS_INFO, "400 MHz FSB\n");
if (cycle <= 0x30) {
drc |= 0x7;
- print_info("333 MHz DDR\n");
+ printk(BIOS_INFO, "333 MHz DDR\n");
} else if (cycle <= 0x3d) {
drc |= 0x0;
- print_info("266 MHz DDR\n");
+ printk(BIOS_INFO, "266 MHz DDR\n");
} else {
drc |= 0x2;
- print_info("200 MHz DDR\n");
+ printk(BIOS_INFO, "200 MHz DDR\n");
}
}
- print_debug("DRC = ");
- print_debug_hex32(drc);
- print_debug("\n");
+ printk(BIOS_DEBUG, "DRC = %08x\n", drc);
return drc;
}
@@ -493,7 +442,7 @@
/* Test if we can read the SPD */
dimm_mask = spd_detect_dimms(ctrl);
if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
- print_err("No memory for this cpu\n");
+ printk(BIOS_ERR, "No memory for this cpu\n");
return;
}
return;
@@ -520,16 +469,12 @@
data32 = 0x00002010;
}
- print_debug("ODT Value = ");
- print_debug_hex32(data32);
- print_debug("\n");
+ printk(BIOS_DEBUG, "ODT Value = %08x\n", data32);
pci_write_config32(ctrl->f0, DDR2ODTC, data32);
for (i = 0; i < 2; i++) {
- print_debug("ODT CS");
- print_debug_hex8(i);
- print_debug("\n");
+ printk(BIOS_DEBUG, "ODT CS%d\n", i);
write32(BAR+DCALADDR, 0x0b840001);
write32(BAR+DCALCSR, 0x80000003 | ((i+1)<<21));
@@ -544,14 +489,11 @@
int i;
for (i = 0x0; i < 0x2a0; i += 4) {
if ((i % 16) == 0) {
- print_debug("\n");
- print_debug_hex16(i);
- print_debug(": ");
+ printk(BIOS_DEBUG, "\n%04x: ", i);
}
- print_debug_hex32(read32(BAR+i));
- print_debug(" ");
+ printk(BIOS_DEBUG, "%08x ", read32(BAR+i));
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
@@ -565,7 +507,7 @@
u32 mode_reg;
mask = spd_detect_dimms(ctrl);
- print_debug("Starting SDRAM Enable\n");
+ printk(BIOS_DEBUG, "Starting SDRAM Enable\n");
/* Set DRAM type and Front Side Bus frequency */
drc = spd_set_dram_controller_mode(ctrl, mask);
@@ -593,9 +535,7 @@
/* Apply NOP */
for (cs = 0; cs < 2; cs++) {
- print_debug("NOP CS");
- print_debug_hex8(cs);
- print_debug("\n");
+ printk(BIOS_DEBUG, "NOP CS%d\n", cs);
udelay(16);
write32(BAR+DCALCSR, (0x00000000 | ((cs+1)<<21)));
write32(BAR+DCALCSR, (0x80000000 | ((cs+1)<<21)));
@@ -606,9 +546,7 @@
/* Apply NOP */
udelay(16);
for (cs = 0; cs < 2; cs++) {
- print_debug("NOP CS");
- print_debug_hex8(cs);
- print_debug("\n");
+ printk(BIOS_DEBUG, "NOP CS%d\n", cs);
write32(BAR + DCALCSR, (0x80000000 | ((cs+1)<<21)));
do data32 = read32(BAR+DCALCSR);
while (data32 & 0x80000000);
@@ -617,9 +555,7 @@
/* Precharge all banks */
udelay(16);
for (cs = 0; cs < 2; cs++) {
- print_debug("Precharge CS");
- print_debug_hex8(cs);
- print_debug("\n");
+ printk(BIOS_DEBUG, "Precharge CS%d\n", cs);
write32(BAR+DCALADDR, 0x04000000);
write32(BAR+DCALCSR, (0x80000002 | ((cs+1)<<21)));
do data32 = read32(BAR+DCALCSR);
@@ -629,9 +565,7 @@
/* EMRS: Enable DLLs, set OCD calibration mode to default */
udelay(16);
for (cs = 0; cs < 2; cs++) {
- print_debug("EMRS CS");
- print_debug_hex8(cs);
- print_debug("\n");
+ printk(BIOS_DEBUG, "EMRS CS%d\n", cs);
write32(BAR+DCALADDR, 0x0b840001);
write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21)));
do data32 = read32(BAR+DCALCSR);
@@ -640,9 +574,7 @@
/* MRS: Reset DLLs */
udelay(16);
for (cs = 0; cs < 2; cs++) {
- print_debug("MRS CS");
- print_debug_hex8(cs);
- print_debug("\n");
+ printk(BIOS_DEBUG, "MRS CS%d\n", cs);
write32(BAR+DCALADDR, mode_reg);
write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21)));
do data32 = read32(BAR+DCALCSR);
@@ -652,9 +584,7 @@
/* Precharge all banks */
udelay(48);
for (cs = 0; cs < 2; cs++) {
- print_debug("Precharge CS");
- print_debug_hex8(cs);
- print_debug("\n");
+ printk(BIOS_DEBUG, "Precharge CS%d\n", cs);
write32(BAR+DCALADDR, 0x04000000);
write32(BAR+DCALCSR, (0x80000002 | ((cs+1)<<21)));
do data32 = read32(BAR+DCALCSR);
@@ -665,9 +595,7 @@
for (i = 0; i < 2; i++) {
udelay(16);
for (cs = 0; cs < 2; cs++) {
- print_debug("Refresh CS");
- print_debug_hex8(cs);
- print_debug("\n");
+ printk(BIOS_DEBUG, "Refresh CS%d\n", cs);
write32(BAR+DCALCSR, (0x80000001 | ((cs+1)<<21)));
do data32 = read32(BAR+DCALCSR);
while (data32 & 0x80000000);
@@ -677,9 +605,7 @@
/* MRS: Set DLLs to normal */
udelay(16);
for (cs = 0; cs < 2; cs++) {
- print_debug("MRS CS");
- print_debug_hex8(cs);
- print_debug("\n");
+ printk(BIOS_DEBUG, "MRS CS%d\n", cs);
write32(BAR+DCALADDR, (mode_reg & ~(1<<24)));
write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21)));
do data32 = read32(BAR+DCALCSR);
@@ -689,9 +615,7 @@
/* EMRS: Enable DLLs */
udelay(16);
for (cs = 0; cs < 2; cs++) {
- print_debug("EMRS CS");
- print_debug_hex8(cs);
- print_debug("\n");
+ printk(BIOS_DEBUG, "EMRS CS%d\n", cs);
write32(BAR+DCALADDR, 0x0b840001);
write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21)));
do data32 = read32(BAR+DCALCSR);
@@ -712,9 +636,7 @@
/* Receive enable calibration */
udelay(16);
for (cs = 0; cs < 1; cs++) {
- print_debug("receive enable calibration CS");
- print_debug_hex8(cs);
- print_debug("\n");
+ printk(BIOS_DEBUG, "receive enable calibration CS%d\n", cs);
write32(BAR+DCALCSR, (0x8000000c | ((cs+1)<<21)));
do data32 = read32(BAR+DCALCSR);
while (data32 & 0x80000000);
@@ -738,18 +660,16 @@
for (cs = 0; cs < 2; cs++) {
if (!(mask & (1<<cs)))
continue;
- print_debug("clear memory CS");
- print_debug_hex8(cs);
- print_debug("\n");
+ printk(BIOS_DEBUG, "clear memory CS%d\n", cs);
write32(BAR+MBCSR, 0xa00000f0 | ((cs+1)<<20) | (0<<16));
do data32 = read32(BAR+MBCSR);
while (data32 & 0x80000000);
if (data32 & 0x40000000)
- print_debug("failed!\n");
+ printk(BIOS_DEBUG, "failed!\n");
}
/* Clear read/write FIFO pointers */
- print_debug("clear read/write fifo pointers\n");
+ printk(BIOS_DEBUG, "clear read/write fifo pointers\n");
write32(BAR+DDRIOMC2, read32(BAR+DDRIOMC2) | (1<<15));
udelay(16);
write32(BAR+DDRIOMC2, read32(BAR+DDRIOMC2) & ~(1<<15));
@@ -757,7 +677,7 @@
dump_dcal_regs();
- print_debug("Done\n");
+ printk(BIOS_DEBUG, "Done\n");
/* Set initialization complete */
drc |= (1 << 29);
diff --git a/src/northbridge/intel/i440bx/debug.c b/src/northbridge/intel/i440bx/debug.c
index ef9d513..efd4326 100644
--- a/src/northbridge/intel/i440bx/debug.c
+++ b/src/northbridge/intel/i440bx/debug.c
@@ -35,34 +35,18 @@
}
}
-static void print_debug_pci_dev(unsigned dev)
-{
- print_debug("PCI: ");
- print_debug_hex8((dev >> 16) & 0xff);
- print_debug_char(':');
- print_debug_hex8((dev >> 11) & 0x1f);
- print_debug_char('.');
- print_debug_hex8((dev >> 8) & 7);
-}
-
void dump_pci_device(unsigned dev)
{
int i;
- print_debug_pci_dev(dev);
- print_debug("\n");
+ printk(BIOS_DEBUG, "PCI: %02x:%02x.%02x\n", (dev >> 20) & 0xff, (dev >> 15) & 0x1f, (dev >> 12) & 7);
for (i = 0; i <= 255; i++) {
unsigned char val;
- if ((i & 0x0f) == 0) {
- print_debug_hex8(i);
- print_debug_char(':');
- }
val = pci_read_config8(dev, i);
- print_debug_char(' ');
- print_debug_hex8(val);
- if ((i & 0x0f) == 0x0f) {
- print_debug("\n");
- }
+ if ((i & 0x0f) == 0)
+ printk(BIOS_DEBUG, "%02x: %02x", i, val);
+ if ((i & 0x0f) == 0x0f)
+ printk(BIOS_DEBUG, "\n");
}
}
#endif
diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c
index e3cfbdf..f191abe 100644
--- a/src/northbridge/intel/i440bx/raminit.c
+++ b/src/northbridge/intel/i440bx/raminit.c
@@ -752,7 +752,7 @@
PRINT_DEBUG("Found DIMM in slot %d\n", i);
if (edo && sd) {
- print_err("Mixing EDO/SDRAM unsupported!\n");
+ printk(BIOS_ERR, "Mixing EDO/SDRAM unsupported!\n");
die("HALT\n");
}
@@ -857,11 +857,11 @@
if (col == 4)
bpr |= 0xc0;
} else {
- print_err("# of banks of DIMM unsupported!\n");
+ printk(BIOS_ERR, "# of banks of DIMM unsupported!\n");
die("HALT\n");
}
if (dra == -1) {
- print_err("Page size not supported\n");
+ printk(BIOS_ERR, "Page size not supported\n");
die("HALT\n");
}
@@ -872,7 +872,7 @@
*/
struct dimm_size sz = spd_get_dimm_size(device);
if ((sz.side1 < 8)) {
- print_err("DIMMs smaller than 8MB per side\n"
+ printk(BIOS_ERR, "DIMMs smaller than 8MB per side\n"
"are not supported on this NB.\n");
die("HALT\n");
}
diff --git a/src/northbridge/intel/i440lx/raminit.c b/src/northbridge/intel/i440lx/raminit.c
index 7d283a1..ddabf25 100644
--- a/src/northbridge/intel/i440lx/raminit.c
+++ b/src/northbridge/intel/i440lx/raminit.c
@@ -32,10 +32,10 @@
/* Debugging macros. */
#if CONFIG_DEBUG_RAM_SETUP
-#define PRINT_DEBUG(x) print_debug(x)
-#define PRINT_DEBUG_HEX8(x) print_debug_hex8(x)
-#define PRINT_DEBUG_HEX16(x) print_debug_hex16(x)
-#define PRINT_DEBUG_HEX32(x) print_debug_hex32(x)
+#define PRINT_DEBUG(x) printk(BIOS_DEBUG, x)
+#define PRINT_DEBUG_HEX8(x) printk(BIOS_DEBUG, "%02x", x)
+#define PRINT_DEBUG_HEX16(x) printk(BIOS_DEBUG, "%04x", x)
+#define PRINT_DEBUG_HEX32(x) printk(BIOS_DEBUG, "%08x", x)
#define DUMPNORTH() dump_pci_device(PCI_DEV(0, 0, 0))
#else
#define PRINT_DEBUG(x)
diff --git a/src/northbridge/intel/i82810/debug.c b/src/northbridge/intel/i82810/debug.c
index c3e4fb9..b74bb36 100644
--- a/src/northbridge/intel/i82810/debug.c
+++ b/src/northbridge/intel/i82810/debug.c
@@ -1,73 +1,52 @@
#include <console/console.h>
#include <arch/io.h>
#include <spd.h>
-#include "i82810.h"
#include "raminit.h"
+#include <spd.h>
+#include <console/console.h>
#if CONFIG_DEBUG_RAM_SETUP
void dump_spd_registers(void)
{
int i;
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
for(i = 0; i < DIMM_SOCKETS; i++) {
unsigned device;
device = DIMM0 + i;
if (device) {
int j;
- print_debug("dimm: ");
- print_debug_hex8(i);
- print_debug(".0: ");
- print_debug_hex8(device);
+ printk(BIOS_DEBUG, "DIMM %d: %02x", i, device);
for(j = 0; j < 256; j++) {
int status;
unsigned char byte;
if ((j & 0xf) == 0) {
- print_debug("\n");
- print_debug_hex8(j);
- print_debug(": ");
+ printk(BIOS_DEBUG, "\n%02x: ", j);
}
status = smbus_read_byte(device, j);
if (status < 0) {
- print_debug("bad device\n");
+ printk(BIOS_DEBUG, "bad device\n");
break;
}
byte = status & 0xff;
- print_debug_hex8(byte);
- print_debug_char(' ');
+ printk(BIOS_DEBUG, "%02x ", byte);
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
}
}
-static void print_debug_pci_dev(unsigned dev)
-{
- print_debug("PCI: ");
- print_debug_hex8((dev >> 16) & 0xff);
- print_debug_char(':');
- print_debug_hex8((dev >> 11) & 0x1f);
- print_debug_char('.');
- print_debug_hex8((dev >> 8) & 7);
-}
-
void dump_pci_device(unsigned dev)
{
int i;
- print_debug_pci_dev(dev);
- print_debug("\n");
+ printk(BIOS_DEBUG, "PCI: %02x:%02x.%02x\n", (dev >> 20) & 0xff, (dev >> 15) & 0x1f, (dev >> 12) & 7);
for (i = 0; i <= 255; i++) {
unsigned char val;
- if ((i & 0x0f) == 0) {
- print_debug_hex8(i);
- print_debug_char(':');
- }
val = pci_read_config8(dev, i);
- print_debug_char(' ');
- print_debug_hex8(val);
- if ((i & 0x0f) == 0x0f) {
- print_debug("\n");
- }
+ if ((i & 0x0f) == 0)
+ printk(BIOS_DEBUG, "%02x: %02x", i, val);
+ if ((i & 0x0f) == 0x0f)
+ printk(BIOS_DEBUG, "\n");
}
}
#endif
diff --git a/src/northbridge/intel/i855/debug.c b/src/northbridge/intel/i855/debug.c
index 327f47d..ed26fad 100644
--- a/src/northbridge/intel/i855/debug.c
+++ b/src/northbridge/intel/i855/debug.c
@@ -22,12 +22,8 @@
static void print_debug_pci_dev(unsigned dev)
{
- print_debug("PCI: ");
- print_debug_hex8((dev >> 20) & 0xff);
- print_debug_char(':');
- print_debug_hex8((dev >> 15) & 0x1f);
- print_debug_char('.');
- print_debug_hex8((dev >> 12) & 0x07);
+ printk(BIOS_DEBUG, "PCI: %02x:%02x.%x",
+ (dev >> 20) & 0xff, (dev >> 15) & 0x1f, (dev >> 12) & 0x07);
}
static inline void print_pci_devices(void)
@@ -44,7 +40,7 @@
continue;
}
print_debug_pci_dev(dev);
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
}
@@ -52,20 +48,16 @@
{
int i;
print_debug_pci_dev(dev);
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
for(i = 0; i <= 255; i++) {
unsigned char val;
- if ((i & 0x0f) == 0) {
- print_debug_hex8(i);
- print_debug_char(':');
- }
+ if ((i & 0x0f) == 0)
+ printk(BIOS_DEBUG, "%02x:", i);
val = pci_read_config8(dev, i);
- print_debug_char(' ');
- print_debug_hex8(val);
- if ((i & 0x0f) == 0x0f) {
- print_debug("\n");
- }
+ printk(BIOS_DEBUG, " %02x", val);
+ if ((i & 0x0f) == 0x0f)
+ printk(BIOS_DEBUG, "\n");
}
}
@@ -89,34 +81,27 @@
static inline void dump_spd_registers(void)
{
int i;
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
for(i = 0; i < 2; i++) {
unsigned device;
device = DIMM0 + i;
if (device) {
int j;
- print_debug("dimm: ");
- print_debug_hex8(i);
- print_debug(".0: ");
- print_debug_hex8(device);
+ printk(BIOS_DEBUG, "dimm: %02x.0: %02x", i, device);
for(j = 0; j < 256; j++) {
int status;
unsigned char byte;
- if ((j & 0xf) == 0) {
- print_debug("\n");
- print_debug_hex8(j);
- print_debug(": ");
- }
+ if ((j & 0xf) == 0)
+ printk(BIOS_DEBUG, "\n%02x: ", j);
status = smbus_read_byte(device, j);
if (status < 0) {
- print_debug("bad device\n");
+ printk(BIOS_DEBUG, "bad device\n");
break;
}
byte = status & 0xff;
- print_debug_hex8(byte);
- print_debug_char(' ');
+ printk(BIOS_DEBUG, "%02x ", byte);
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
}
}
@@ -124,30 +109,25 @@
static inline void dump_smbus_registers(void)
{
int i;
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
for(i = 1; i < 0x80; i++) {
unsigned device;
device = i;
int j;
- print_debug("smbus: ");
- print_debug_hex8(device);
+ printk(BIOS_DEBUG, "smbus: %02x", device);
for(j = 0; j < 256; j++) {
int status;
unsigned char byte;
- if ((j & 0xf) == 0) {
- print_debug("\n");
- print_debug_hex8(j);
- print_debug(": ");
- }
+ if ((j & 0xf) == 0)
+ printk(BIOS_DEBUG, "\n%02x: ", j);
status = smbus_read_byte(device, j);
if (status < 0) {
- print_debug("bad device\n");
+ printk(BIOS_DEBUG, "bad device\n");
break;
}
byte = status & 0xff;
- print_debug_hex8(byte);
- print_debug_char(' ');
+ printk(BIOS_DEBUG, "%02x ", byte);
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
}
diff --git a/src/northbridge/intel/i855/raminit.c b/src/northbridge/intel/i855/raminit.c
index 0ab4d38..39e12d2 100644
--- a/src/northbridge/intel/i855/raminit.c
+++ b/src/northbridge/intel/i855/raminit.c
@@ -415,7 +415,7 @@
{
int i;
- print_debug("Ram enable 1\n");
+ printk(BIOS_DEBUG, "Ram enable 1\n");
delay();
delay();
@@ -433,16 +433,16 @@
delay();
delay();
- print_debug("Ram enable 4\n");
+ printk(BIOS_DEBUG, "Ram enable 4\n");
do_ram_command(RAM_COMMAND_EMRS, SDRAM_EXTMODE_DLL_ENABLE);
delay();
delay();
delay();
- print_debug("Ram enable 5\n");
+ printk(BIOS_DEBUG, "Ram enable 5\n");
do_ram_command(RAM_COMMAND_MRS, VG85X_MODE | SDRAM_MODE_DLL_RESET);
- print_debug("Ram enable 6\n");
+ printk(BIOS_DEBUG, "Ram enable 6\n");
do_ram_command(RAM_COMMAND_PRECHARGE, 0);
delay();
delay();
@@ -457,7 +457,7 @@
delay();
}
- print_debug("Ram enable 8\n");
+ printk(BIOS_DEBUG, "Ram enable 8\n");
do_ram_command(RAM_COMMAND_MRS, VG85X_MODE | SDRAM_MODE_NORMAL);
/* Set GME-M Mode Select bits back to NORMAL operation mode */
@@ -467,7 +467,7 @@
delay();
delay();
- print_debug("Ram enable 9\n");
+ printk(BIOS_DEBUG, "Ram enable 9\n");
set_initialize_complete();
delay();
@@ -476,11 +476,11 @@
delay();
delay();
- print_debug("After configuration:\n");
+ printk(BIOS_DEBUG, "After configuration:\n");
/* dump_pci_devices(); */
/*
- print_debug("\n\n***** RAM TEST *****\n");
+ printk(BIOS_DEBUG, "\n\n***** RAM TEST *****\n");
ram_check(0, 0xa0000);
ram_check(0x100000, 0x40000000);
*/
@@ -497,7 +497,7 @@
static void sdram_set_registers(void)
{
/*
- print_debug("Before configuration:\n");
+ printk(BIOS_DEBUG, "Before configuration:\n");
dump_pci_devices();
*/
}
@@ -572,13 +572,13 @@
die_on_spd_error(value);
value &= 0x7f; // Mask off self-refresh bit
if (value > MAX_SPD_REFRESH_RATE) {
- print_err("unsupported refresh rate\n");
+ printk(BIOS_ERR, "unsupported refresh rate\n");
continue;
}
// Get the appropriate i855 refresh mode for this DIMM
dimm_refresh_mode = refresh_rate_map[value];
if (dimm_refresh_mode > 7) {
- print_err("unsupported refresh rate\n");
+ printk(BIOS_ERR, "unsupported refresh rate\n");
continue;
}
// If this DIMM requires more frequent refresh than others,
@@ -965,7 +965,7 @@
dimm_mask = spd_get_supported_dimms();
if (dimm_mask == 0) {
- print_debug("No usable memory for this controller\n");
+ printk(BIOS_DEBUG, "No usable memory for this controller\n");
} else {
PRINTK_DEBUG("DIMM MASK: %02x\n", dimm_mask);
diff --git a/src/northbridge/intel/i945/debug.c b/src/northbridge/intel/i945/debug.c
index e47f762..397bd4b 100644
--- a/src/northbridge/intel/i945/debug.c
+++ b/src/northbridge/intel/i945/debug.c
@@ -109,12 +109,12 @@
void dump_mem(unsigned start, unsigned end)
{
unsigned i;
- print_debug("dump_mem:");
+ printk(BIOS_DEBUG, "dump_mem:");
for(i=start;i<end;i++) {
if((i & 0xf)==0) {
printk(BIOS_DEBUG, "\n%08x:", i);
}
printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i));
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}