commit | d367503147125210fbc09fa43628d233840f2c65 | [log] [tgz] |
---|---|---|
author | Surendranath Gurivireddy <surendranath.r.gurivireddy@intel.com> | Thu Oct 31 15:45:39 2019 -0700 |
committer | Patrick Georgi <pgeorgi@google.com> | Wed Nov 27 13:50:14 2019 +0000 |
tree | 35dfbcf5eee97f09d7f51b37bd2e0be351effc8a | |
parent | b0f15f0f86b13257fdbf3ce2c2c651c40116994c [diff] |
soc/intel/cannonlake: Disable USB2 PHY Power gating Workaround to disable USB2 PHY power gating to fix issue seen when Apple 87W USB-C charger is connected in S0ix state on WHL platforms (based on Intel's recommendation). Issue is seen on CML platforms also. So, disable power gating for Drallion too. Add devicetree entry to set the flag to disable USB2 PHY power gating for different CNL PCH based platforms BUG=b:133775942 TEST=Connect Apple 87W USB-C charger when the system is in sleep and check if the system wakes up after that Signed-off-by: Surendranath Gurivireddy <surendranath.r.gurivireddy@intel.com> Change-Id: I95909c73de758fccc7f616a330c1e1f0667e8c25 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36519 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAIN
Kconfig option if you're feeling lucky (no support in this case).Optional:
make menuconfig
and make nconfig
)Please consult https://www.coreboot.org/Build_HOWTO for details.
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.