diff --git a/src/northbridge/intel/x4x/ram_calc.c b/src/northbridge/intel/x4x/ram_calc.c
index 49afdc3..1f1c13f 100644
--- a/src/northbridge/intel/x4x/ram_calc.c
+++ b/src/northbridge/intel/x4x/ram_calc.c
@@ -93,7 +93,7 @@
 }
 
 /* Depending of UMA and TSEG configuration, TSEG might start at any
- * 1 MiB aligment. As this may cause very greedy MTRR setup, push
+ * 1 MiB alignment. As this may cause very greedy MTRR setup, push
  * CBMEM top downwards to 4 MiB boundary.
  */
 void *cbmem_top(void)