diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c
index b406096..3f83e08 100644
--- a/src/soc/intel/baytrail/southcluster.c
+++ b/src/soc/intel/baytrail/southcluster.c
@@ -328,9 +328,9 @@
 	 * that requires setting up the 64-bit BAR. */
 	pci_write_config32(dev, PCI_BASE_ADDRESS_0, TEMP_BASE_ADDRESS);
 	pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0);
-	pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
+	pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
 	write32(gctl, read32(gctl) | 0x1);
-	pci_write_config8(dev, PCI_COMMAND, 0);
+	pci_write_config16(dev, PCI_COMMAND, 0);
 	pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0);
 }
 
@@ -452,7 +452,7 @@
 /* Common PCI device function disable. */
 void southcluster_enable_dev(struct device *dev)
 {
-	uint32_t reg32;
+	uint16_t reg16;
 
 	if (!dev->enabled) {
 		int slot = PCI_SLOT(dev->path.pci.devfn);
@@ -461,10 +461,10 @@
 		       dev_path(dev), slot, func);
 
 		/* Ensure memory, io, and bus master are all disabled */
-		reg32 = pci_read_config32(dev, PCI_COMMAND);
-		reg32 &= ~(PCI_COMMAND_MASTER |
+		reg16 = pci_read_config16(dev, PCI_COMMAND);
+		reg16 &= ~(PCI_COMMAND_MASTER |
 			   PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
-		pci_write_config32(dev, PCI_COMMAND, reg32);
+		pci_write_config16(dev, PCI_COMMAND, reg16);
 
 		/* Place device in D3Hot */
 		if (place_device_in_d3hot(dev) < 0) {
@@ -477,9 +477,7 @@
 		sc_disable_devfn(dev);
 	} else {
 		/* Enable SERR */
-		reg32 = pci_read_config32(dev, PCI_COMMAND);
-		reg32 |= PCI_COMMAND_SERR;
-		pci_write_config32(dev, PCI_COMMAND, reg32);
+		pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR);
 	}
 }