commit 6453cffd215666162fdee2d9cb0660b7ff68dcc7
author Bo-Chen Chen <rex-bc.chen@mediatek.com> Mon Jan 30 18:58:01 2023 +0800
committer Paul Fagerburg <pfagerburg@chromium.org> Wed Feb 01 14:59:11 2023 +0000
tree 870d812cd99da18d789bf1ec1788c804c67c71b0
parent 0bff4b05b8800aa1bca5ef43732bf9ead859a304

mb/google/geralt: Add USB3 HUB reset funtion to bootblock

After powering on the device, we need to pull USB3_HUB_RST_L up to
enable USB3 Hub.

TEST=boot kernel from USB ok
BUG=b:264841530

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com>
Change-Id: I8df35efb78e90a5b3314840fe2eae81d6e501242
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72594
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/google/geralt/bootblock.c

diff --git a/src/mainboard/google/geralt/bootblock.c b/src/mainboard/google/geralt/bootblock.c
index 4476aab..2bd69ad 100644
--- a/src/mainboard/google/geralt/bootblock.c
+++ b/src/mainboard/google/geralt/bootblock.c
@@ -2,12 +2,18 @@
 
 #include <bootblock_common.h>
 #include <device/mmio.h>
+#include <gpio.h>
 #include <soc/gpio.h>
 #include <soc/i2c.h>
 #include <soc/spi.h>
 
 #include "gpio.h"
 
+static void usb3_hub_reset(void)
+{
+	gpio_output(GPIO_USB3_HUB_RST_L, 1);
+}
+
 void bootblock_mainboard_init(void)
 {
 	mtk_i2c_bus_init(CONFIG_DRIVER_TPM_I2C_BUS, I2C_SPEED_FAST);
@@ -15,4 +21,5 @@
 	mtk_snfc_init();
 	setup_chromeos_gpios();
 	gpio_eint_configure(GPIO_GSC_AP_INT_ODL, IRQ_TYPE_EDGE_RISING);
+	usb3_hub_reset();
 }

src/mainboard/google/geralt/gpio.h

diff --git a/src/mainboard/google/geralt/gpio.h b/src/mainboard/google/geralt/gpio.h
index 3793779..7eec8f1 100644
--- a/src/mainboard/google/geralt/gpio.h
+++ b/src/mainboard/google/geralt/gpio.h
@@ -22,6 +22,8 @@
 
 #define GPIO_SD_CD_ODL			GPIO(I2SIN_MCK)
 
+#define GPIO_USB3_HUB_RST_L		GPIO(MSDC2_DAT0)
+
 void setup_chromeos_gpios(void);
 
 #endif