commit | 86302a806c5cc9b575424305e761753710417692 | [log] [tgz] |
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author | Raul E Rangel <rrangel@chromium.org> | Tue Jan 18 15:29:54 2022 -0700 |
committer | Raul Rangel <rrangel@chromium.org> | Sun Jan 23 16:42:48 2022 +0000 |
tree | 6d3c1305d29ad1a9369770e7a9a2ac03b03c4f4b | |
parent | 1e1aa0ca4d4d5ae9d0b4917220cc72f9c441b8a2 [diff] |
soc/amd/{common,cezanne,picasso}: Add PRE_X86_CBMEM_CONSOLE_SIZE This change splits the size of the console transfer region and size of the bootblock/romstage Pre-RAM console region. This allows having a larger Pre-RAM console while not impacting the size of the PSP verstage console. Instead of directly using the PRE_X86_CBMEM_CONSOLE_SIZE symbol in `setup_cbmem_console`, I chose to use the offsets provided in the transfer buffer. It would be nice to eventually do this for all the fields in the transfer buffer. BUG=b:213828947 TEST=Boot guybrush and verify verstage logs are no longer truncated Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I8b8cc46600192a7db00f5c1f24c3c8304c4db31d Reviewed-on: https://review.coreboot.org/c/coreboot/+/61189 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAIN
Kconfig option if you're feeling lucky (no support in this case).Optional:
make menuconfig
and make nconfig
)Please consult https://www.coreboot.org/Build_HOWTO for details.
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.