soc/amd/stoneyridge: Remove double defined GPIO MMIO bases

GPIO control a mux base addresses are defined within MMIO definitions
and again bellow as GPIO specific base addresses. Eliminate those outside
MMIO bases. Rename them to something indicating that they are both MMIO
and related to GPIO.

BUG=b:117754420
TEST=Build grunt.

Change-Id: I53f7cf17d6267e6f8daa650b5f864bab688dc3f0
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29156
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/amd/stoneyridge/acpi/gpio_lib.asl b/src/soc/amd/stoneyridge/acpi/gpio_lib.asl
index fbd6525..d18b147 100644
--- a/src/soc/amd/stoneyridge/acpi/gpio_lib.asl
+++ b/src/soc/amd/stoneyridge/acpi/gpio_lib.asl
@@ -19,7 +19,7 @@
 Method (GPAD, 0x1)
 {
 	/* Arg0 - GPIO pin number */
-	Return (Add(Multiply(Arg0, 4), GPIO_CONTROL_BASE))
+	Return (Add(Multiply(Arg0, 4), GPIO_CONTROL_MMIO_BASE))
 }
 
 /* Read pin control dword */
diff --git a/src/soc/amd/stoneyridge/gpio.c b/src/soc/amd/stoneyridge/gpio.c
index cc54f2c..3eaa3a0 100644
--- a/src/soc/amd/stoneyridge/gpio.c
+++ b/src/soc/amd/stoneyridge/gpio.c
@@ -237,7 +237,7 @@
 		control = gpio_list_ptr[index].control;
 		control_flags = gpio_list_ptr[index].flags;
 
-		mux_ptr = (uint8_t *)(uintptr_t)(gpio + AMD_GPIO_MUX);
+		mux_ptr = (uint8_t *)(uintptr_t)(gpio + GPIO_IOMUX_MMIO_BASE);
 		write8(mux_ptr, mux & AMD_GPIO_MUX_MASK);
 		read8(mux_ptr); /* Flush posted write */
 		/* special case if pin 2 is assigned to wake */
@@ -323,7 +323,7 @@
 	uint32_t *gpio_ptr;
 	uint8_t *mux_ptr;
 
-	mux_ptr = (uint8_t *)(uintptr_t)(gpio + AMD_GPIO_MUX);
+	mux_ptr = (uint8_t *)(uintptr_t)(gpio + GPIO_IOMUX_MMIO_BASE);
 	gpio_ptr = (uint32_t *)gpio_get_address(gpio);
 	save_table->mux_value = read8(mux_ptr);
 	save_table->control_value = read32(gpio_ptr);
@@ -335,7 +335,7 @@
 	uint32_t *gpio_ptr;
 	uint8_t *mux_ptr;
 
-	mux_ptr = (uint8_t *)(uintptr_t)(gpio + AMD_GPIO_MUX);
+	mux_ptr = (uint8_t *)(uintptr_t)(gpio + GPIO_IOMUX_MMIO_BASE);
 	gpio_ptr = (uint32_t *)gpio_get_address(gpio);
 	write8(mux_ptr, save_table->mux_value);
 	read8(mux_ptr);
diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h
index beb2bc8..3e86564 100644
--- a/src/soc/amd/stoneyridge/include/soc/iomap.h
+++ b/src/soc/amd/stoneyridge/include/soc/iomap.h
@@ -37,10 +37,10 @@
 #define APU_SMI_BASE			0xfed80200
 #define PM_MMIO_BASE			0xfed80300
 #define BIOSRAM_MMIO_BASE		0xfed80500
-#define IOMUX_MMIO_BASE			0xfed80d00
+#define GPIO_IOMUX_MMIO_BASE		0xfed80d00
 #define MISC_MMIO_BASE			0xfed80e00
-#define GPIO_CONTROL_BASE		0xfed81500
 #define XHCI_ACPI_PM_MMIO_BASE		0xfed81c00
+#define GPIO_CONTROL_MMIO_BASE		0xfed81500
 #define AOAC_MMIO_BASE			0xfed81e00
 
 #define APU_UART0_BASE			0xfedc6000
@@ -71,10 +71,6 @@
 #define AB_DATA				(AB_INDX+4)
 #define SYS_RESET			0xcf9
 
-/* GPIO control and mux access */
-#define AMD_GPIO_MUX			(AMD_SB_ACPI_MMIO_ADDR + 0x00000d00)
-#define AMD_GPIO_CONTROL		(AMD_SB_ACPI_MMIO_ADDR + 0x00001500)
-
 /* BiosRam Ranges at 0xfed80500 or I/O 0xcd4/0xcd5 */
 #define BIOSRAM_CBMEM_TOP		0xf0 /* 4 bytes */
 #define BIOSRAM_UMA_SIZE		0xf4 /* 4 bytes */