commit 62b23c10e03fb713bdd9caf888c52c89ee79fb66
author Elyes HAOUAS <ehaouas@noos.fr> Wed Jan 26 07:43:51 2022 +0100
committer Felix Held <felix-coreboot@felixheld.de> Thu Jan 27 14:48:20 2022 +0000
tree 5ffedb5b44c59633366790c1c6f476ab490fcc39
parent 30f05c4e7caa52e03260c77261776f700e8bb511

nb/intel/sandybridge/raminit_mrc.c: Use <smbios.h> macros

Use macros defined in <smbios.h> for 'ddr_type' and 'bus_width'

Change-Id: I0501147139387cd9b5c7ec6b7ba7f8a5c5bd18bb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

src/northbridge/intel/sandybridge/raminit_mrc.c

diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c
index 186ab59..0a7d192 100644
--- a/src/northbridge/intel/sandybridge/raminit_mrc.c
+++ b/src/northbridge/intel/sandybridge/raminit_mrc.c
@@ -14,6 +14,7 @@
 #include <device/pci_def.h>
 #include <lib.h>
 #include <mrc_cache.h>
+#include <smbios.h>
 #include <stddef.h>
 #include <stdint.h>
 #include <timestamp.h>
@@ -413,7 +414,7 @@
 		if (dimm_size) {
 			dimm = &mem_info->dimm[dimm_cnt];
 			dimm->dimm_size = dimm_size;
-			dimm->ddr_type = 0x18;				/* DDR3 */
+			dimm->ddr_type = MEMORY_TYPE_DDR3;
 			dimm->ddr_frequency = ddr_frequency;
 			dimm->rank_per_dimm = 1 + ((ch_conf >> 17) & 1);
 			dimm->channel_num = i;
@@ -429,7 +430,7 @@
 				(pei_data->spd_data[0][118] << 8) |
 				(pei_data->spd_data[0][117] & 0xFF);
 			dimm->mod_type = 3;				/* SPD_SODIMM */
-			dimm->bus_width = 0x3;				/* 64-bit */
+			dimm->bus_width = MEMORY_BUS_WIDTH_64;
 			dimm_cnt++;
 		}
 		/* DIMM-B */
@@ -437,7 +438,7 @@
 		if (dimm_size) {
 			dimm = &mem_info->dimm[dimm_cnt];
 			dimm->dimm_size = dimm_size;
-			dimm->ddr_type = 0x18;				/* DDR3 */
+			dimm->ddr_type = MEMORY_TYPE_DDR3;
 			dimm->ddr_frequency = ddr_frequency;
 			dimm->rank_per_dimm =  1 + ((ch_conf >> 18) & 1);
 			dimm->channel_num = i;
@@ -453,7 +454,7 @@
 				(pei_data->spd_data[0][118] << 8) |
 				(pei_data->spd_data[0][117] & 0xFF);
 			dimm->mod_type = 3;				/* SPD_SODIMM */
-			dimm->bus_width = 0x3;				/* 64-bit */
+			dimm->bus_width = MEMORY_BUS_WIDTH_64;
 			dimm_cnt++;
 		}
 	}