commit 6237175ed5ef29a0e9b82cc7268ca424c5bb44ea
author Angel Pons <th3fanbus@gmail.com> Sat Mar 27 21:13:44 2021 +0100
committer Patrick Georgi <pgeorgi@google.com> Sun May 02 21:56:00 2021 +0000
tree 4f60ba095f7716baa777e7b93305c16418915d4a
parent 9fa141898e49a844864cfc00f1ddc4c4e1981c2a

nb/intel/haswell: Uniformize include guards

Remove leading and trailing underscores and change `RAMINIT_H` to be
more consistent with other headers.

Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.

Change-Id: Ie20fcaa0f9393eb0a34054eda53b9bade63cc0d2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51890
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/northbridge/intel/haswell/registers/dmibar.h

diff --git a/src/northbridge/intel/haswell/registers/dmibar.h b/src/northbridge/intel/haswell/registers/dmibar.h
index 9d52382..09a9078 100644
--- a/src/northbridge/intel/haswell/registers/dmibar.h
+++ b/src/northbridge/intel/haswell/registers/dmibar.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef __HASWELL_REGISTERS_DMIBAR_H__
-#define __HASWELL_REGISTERS_DMIBAR_H__
+#ifndef HASWELL_REGISTERS_DMIBAR_H
+#define HASWELL_REGISTERS_DMIBAR_H
 
 #define DMIVCECH	0x000	/* 32bit */
 #define DMIPVCCAP1	0x004	/* 32bit */
@@ -53,4 +53,4 @@
 
 #define DMI_AFE_PM_TMR	0xc28	/* 32bit */
 
-#endif /* __HASWELL_REGISTERS_DMIBAR_H__ */
+#endif /* HASWELL_REGISTERS_DMIBAR_H */

src/northbridge/intel/haswell/registers/epbar.h

diff --git a/src/northbridge/intel/haswell/registers/epbar.h b/src/northbridge/intel/haswell/registers/epbar.h
index 699a2ba..cccfcca 100644
--- a/src/northbridge/intel/haswell/registers/epbar.h
+++ b/src/northbridge/intel/haswell/registers/epbar.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef __HASWELL_REGISTERS_EPBAR_H__
-#define __HASWELL_REGISTERS_EPBAR_H__
+#ifndef HASWELL_REGISTERS_EPBAR_H
+#define HASWELL_REGISTERS_EPBAR_H
 
 #define EPPVCCAP1	0x004	/* 32bit */
 #define EPPVCCAP2	0x008	/* 32bit */
@@ -25,4 +25,4 @@
 #define EPLE4D		0x080	/* 32bit */
 #define EPLE4A		0x088	/* 64bit */
 
-#endif /* __HASWELL_REGISTERS_EPBAR_H__ */
+#endif /* HASWELL_REGISTERS_EPBAR_H */

src/northbridge/intel/haswell/registers/host_bridge.h

diff --git a/src/northbridge/intel/haswell/registers/host_bridge.h b/src/northbridge/intel/haswell/registers/host_bridge.h
index 7746801..1ee0ab2 100644
--- a/src/northbridge/intel/haswell/registers/host_bridge.h
+++ b/src/northbridge/intel/haswell/registers/host_bridge.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef __HASWELL_REGISTERS_HOST_BRIDGE_H__
-#define __HASWELL_REGISTERS_HOST_BRIDGE_H__
+#ifndef HASWELL_REGISTERS_HOST_BRIDGE_H
+#define HASWELL_REGISTERS_HOST_BRIDGE_H
 
 #define EPBAR		0x40
 #define MCHBAR		0x48
@@ -71,4 +71,4 @@
 
 #define CAPID0_B	0xe8
 
-#endif /* __HASWELL_REGISTERS_HOST_BRIDGE_H__ */
+#endif /* HASWELL_REGISTERS_HOST_BRIDGE_H */

src/northbridge/intel/haswell/registers/mchbar.h

diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h
index 2dfad62..5610e70 100644
--- a/src/northbridge/intel/haswell/registers/mchbar.h
+++ b/src/northbridge/intel/haswell/registers/mchbar.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef __HASWELL_REGISTERS_MCHBAR_H__
-#define __HASWELL_REGISTERS_MCHBAR_H__
+#ifndef HASWELL_REGISTERS_MCHBAR_H
+#define HASWELL_REGISTERS_MCHBAR_H
 
 /* Memory controller characteristics */
 #define NUM_CHANNELS	2
@@ -74,4 +74,4 @@
 #define CRDTLCK			0x77fc
 #define MCARBLCK		0x7ffc
 
-#endif /* __HASWELL_REGISTERS_MCHBAR_H__ */
+#endif /* HASWELL_REGISTERS_MCHBAR_H */