tree fca3920033f33bc512af9772fb2a746e255744e1
parent 76ef18d8ffa97844a09268c7459c7fcf0a5f10af
author Cliff Huang <cliff.huang@intel.corp-partner.google.com> 1651194414 -0700
committer Felix Held <felix-coreboot@felixheld.de> 1654781978 +0000

soc/intel/alderlake: Add support for PCIe slot & device detect timeout

1. add timeout for root port detection and pass to FSP.
2. add 'slot implemented' flag and pass to FSP.
3. PcieRpSlotImplemented needs to be set when the root port is set to
hotplug. There is an assertion in FSP checking this.
4. PcieRpSlotImplemented is updated only when it is built-in as it is
default to slot implemented in FSP.

BRANCH=firmware-brya-14505.B

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I13feb1d2d67eaba634a3e700685132fba39e1525
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>