commit 616be8cd1fbdfa77caa02fa77eabe7b9edc9dc36
author Elyes Haouas <ehaouas@noos.fr> Sat Jul 16 09:50:29 2022 +0200
committer Felix Held <felix-coreboot@felixheld.de> Mon Jul 18 11:21:35 2022 +0000
tree 60dc7c808877a1e60a173b25f2558fa97c5bb96e
parent 4d7285df1d3c7e48100ed39b030b67a7bcf07d0e

sb/amd/cimx: Fix some white spaces issues

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Iba81be8ec48fa744f3263e340267a56158656a8f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

src/southbridge/amd/cimx/sb800/spi.c

diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c
index 38439d0..792a4a1 100644
--- a/src/southbridge/amd/cimx/sb800/spi.c
+++ b/src/southbridge/amd/cimx/sb800/spi.c
@@ -29,7 +29,7 @@
 	write8((void *)(spibar + 2), read8((void *)(spibar + 2)) | 1);
 
 	while ((read8((void *)(spibar + 2)) & 1) &&
-	       (read8((void *)(spibar+3)) & 0x80));
+	       (read8((void *)(spibar + 3)) & 0x80));
 }
 
 void spi_init(void)
@@ -98,9 +98,9 @@
 	u8	reg0_val = 0;		/* clear response register */
 	u8	reg1_val = 0xB4;	/* request ownership flag */
 
-	WriteECmsg (MSG_REG0, AccWidthUint8, &reg0_val);
-	WriteECmsg (MSG_REG1, AccWidthUint8, &reg1_val);
-	WriteECmsg (MSG_SYS_TO_IMC, AccWidthUint8, &cmd_val);
+	WriteECmsg(MSG_REG0, AccWidthUint8, &reg0_val);
+	WriteECmsg(MSG_REG1, AccWidthUint8, &reg1_val);
+	WriteECmsg(MSG_SYS_TO_IMC, AccWidthUint8, &cmd_val);
 
 	WaitForEcLDN9MailboxCmdAck();
 }
@@ -111,9 +111,9 @@
 	u8	reg0_val = 0;		/* clear response register */
 	u8	reg1_val = 0xB5;	/* release ownership flag */
 
-	WriteECmsg (MSG_REG0, AccWidthUint8, &reg0_val);
-	WriteECmsg (MSG_REG1, AccWidthUint8, &reg1_val);
-	WriteECmsg (MSG_SYS_TO_IMC, AccWidthUint8, &cmd_val);
+	WriteECmsg(MSG_REG0, AccWidthUint8, &reg0_val);
+	WriteECmsg(MSG_REG1, AccWidthUint8, &reg1_val);
+	WriteECmsg(MSG_SYS_TO_IMC, AccWidthUint8, &cmd_val);
 
 	WaitForEcLDN9MailboxCmdAck();
 }