diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c
index 34d759f..3d05f8e 100644
--- a/src/northbridge/intel/sandybridge/romstage.c
+++ b/src/northbridge/intel/sandybridge/romstage.c
@@ -103,6 +103,9 @@
 	s3resume = southbridge_detect_s3_resume();
 
 	post_code(0x38);
+
+	mainboard_early_init(s3resume);
+
 	/* Enable SPD ROMs and DDR-III DRAM */
 	enable_smbus();