| commit | 609bd9445ed1cc76496a9d65ad1d158904d3cf47 | [log] [tgz] |
|---|---|---|
| author | Vladimir Serbinenko <phcoder@gmail.com> | Sun Jan 31 14:00:54 2016 +0100 |
| committer | Martin Roth <martinroth@google.com> | Tue Feb 09 20:35:40 2016 +0100 |
| tree | b8ddb349366231d819e828cc8bf785f6da3d7e5d | |
| parent | bf725b48f730b5996cf1ee7e5ac84ebc0ec78460 [diff] |
ivy: Add a possiblity for mainboard early init. This is needed for stout EC init. Change-Id: I5c73499c17763229840152a473a2d820802ee2f6 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13535 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
diff --git a/src/northbridge/intel/sandybridge/raminit_native.h b/src/northbridge/intel/sandybridge/raminit_native.h index bfdbe8d..b41aa85 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.h +++ b/src/northbridge/intel/sandybridge/raminit_native.h
@@ -24,5 +24,6 @@ void mainboard_get_spd(spd_raw_data *spd); void rcba_config(void); void pch_enable_lpc(void); +void mainboard_early_init(int s3resume); #endif /* RAMINIT_H */
diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 34d759f..3d05f8e 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c
@@ -103,6 +103,9 @@ s3resume = southbridge_detect_s3_resume(); post_code(0x38); + + mainboard_early_init(s3resume); + /* Enable SPD ROMs and DDR-III DRAM */ enable_smbus();