| commit | 606f4f6c2d2ab4e913bedcd9b2d4ca3c15215778 | [log] [tgz] |
|---|---|---|
| author | Elyes Haouas <ehaouas@noos.fr> | Sun Oct 02 14:34:03 2022 +0200 |
| committer | Martin Roth <martin.roth@amd.corp-partner.google.com> | Thu Oct 06 17:02:21 2022 +0000 |
| tree | f6ee192a23f451a937d55ee344db7019f0b0e48f | |
| parent | 07ad894195c3c5d68eda9f0cbde871166c3d28dc [diff] |
sb/intel/common/early_smbus.h: Add <device/pci_type.h> Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Icf459f07948cd29eb251b49fcecefb98c5f5f259 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68047 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
diff --git a/src/southbridge/intel/common/early_smbus.h b/src/southbridge/intel/common/early_smbus.h index d6a7cbb..0dc32c0 100644 --- a/src/southbridge/intel/common/early_smbus.h +++ b/src/southbridge/intel/common/early_smbus.h
@@ -4,6 +4,7 @@ #define SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS_H #include <device/pci_def.h> +#include <device/pci_type.h> #define PCI_DEV_SMBUS PCI_DEV(0, 0x1f, 3)