haswell: cbmem_get_table_location() implementation
Provide the implemenation of cbmem_get_table_location() so that
cbmem can be initialized early in ramstage when CONFIG_EARLY_CBMEM_INIT
is enabled. The cbmem tables are located just below the TSEG region.
Change-Id: Ia160ac6aff583fc52bf403d047529aaa07088085
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2798
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c
index c8c1704..23bbd29 100644
--- a/src/northbridge/intel/haswell/northbridge.c
+++ b/src/northbridge/intel/haswell/northbridge.c
@@ -418,10 +418,6 @@
mmio_resource(dev, index++, CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10,
CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10);
#endif
-
- /* Leave some space for ACPI, PIRQ and MP tables */
- high_tables_size = HIGH_MEMORY_SIZE;
- high_tables_base = mc_values[TSEG_REG] - high_tables_size;
}
static void mc_read_resources(device_t dev)
@@ -546,6 +542,21 @@
MCHBAR32(0x5500) = 0x00100001;
}
+#if CONFIG_EARLY_CBMEM_INIT
+int cbmem_get_table_location(uint64_t *tables_base, uint64_t *tables_size)
+{
+ uint32_t tseg;
+
+ /* Put the CBMEM location just below TSEG. */
+ *tables_size = HIGH_MEMORY_SIZE;
+ tseg = (pci_read_config32(dev_find_slot(0, PCI_DEVFN(0, 0)),
+ TSEG) & ~((1 << 20) - 1)) - HIGH_MEMORY_SIZE;
+ *tables_base = tseg;
+
+ return 0;
+}
+#endif
+
static void northbridge_enable(device_t dev)
{
#if CONFIG_HAVE_ACPI_RESUME