tree d0137bc591e58a173eada5fe44867502ffd16ca9
parent 61decb0dbf625f35912027e0b49546e6416a8839
author Subrata Banik <subratabanik@google.com> 1680006267 +0530
committer Felix Held <felix-coreboot@felixheld.de> 1680183306 +0000

soc/intel/alderlake: Avoid reprogramming the SRAM BAR

This patch avoids the redundant programming of SRAM BAR when
the SRAM PCI device is enabled. Rather read the PCH SRAM Base
Address Register while enabling crashlog feature.

Additionally, this patch relies on PCI enumeration to get the
SRAM BAR rather than hijacking the SPI temporary base address
which might have resulted in problems if SPI is disabled on
some platform with BAR being implemented.

TEST=Able to build and boot google/marasov and crashlog is working.

Change-Id: I8eb256aa63bbf7222f67cd16a160e71cfb89875a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>