commit 601da481b5437c7a73f97a1bece5990a393037d8
author Damien Zammit <damien@zamaudio.com> Mon May 26 23:00:23 2014 +1000
committer Idwer Vollering <vidwer@gmail.com> Wed Jun 11 03:05:01 2014 +0200
tree bbc60c032786ac6a1b9d8edb4c9b5716ceb6aaea
parent 0240f9492b79509c5b679190853405dc218244f0

util/inteltool: Add pci ids for 4 northbridge models instead of 1.

This patch supports northbridges: 0x0150 0x0154 0x0158 0x015c as 3rd gen core.
Tested on 0x0150 (0x0154 previously only model).

Change-Id: I53a33d864494dd4ac1cb9e8330450f56001ed92c
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: http://review.coreboot.org/5873
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

util/inteltool/pcie.c

diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c
index cafd34a..346d51a 100644
--- a/util/inteltool/pcie.c
+++ b/util/inteltool/pcie.c
@@ -239,7 +239,10 @@
 	case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN:
 		dmi_registers = sandybridge_dmi_registers;
 		size = ARRAY_SIZE(sandybridge_dmi_registers);
-	case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN: /* pretty printing not implemented yet */
+	case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_A: /* pretty printing not implemented yet */
+	case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_B:
+	case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_C:
+	case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_D:
 		dmibar_phys = pci_read_long(nb, 0x68);
 		dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32;
 		dmibar_phys &= 0x0000007ffffff000UL; /* 38:12 */