soc/intel/skylake: Add FSP 2.0 support in romstage
Populate SoC related Memory initialization params.
Post memory init, set DISB, setup stack and MTRRs using the postcar
funtions provided in postcar_loader.c.
TEST=Build and boot kunimitsu, dram initialization done.
ramstage is loaded.
Change-Id: I8d943e29b6e118986189166d92c7891ab6642193
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/16315
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
8 files changed