# SPDX-License-Identifier: GPL-2.0-or-later
fw_config
	field TOUCHPAD 26
		option REGULAR_TOUCHPAD 1
		option NUMPAD_TOUCHPAD 0
	end
end

chip soc/amd/picasso

	# Set FADT Configuration
	register "common_config.fadt_boot_arch" = "ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042"
	# See table 5-34 ACPI 6.3 spec
	register "common_config.fadt_flags" = "ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_SEALED_CASE"

	# ACP Configuration
	register "common_config.acp_config" = "{
		.acp_pin_cfg = I2S_PINS_I2S_TDM,
		.acp_i2s_wake_enable = 0,
		.acp_pme_enable = 0,
	}"

	# Start : OPN Performance Configuration
	# (Configuratin that is common for all variants)
	# For the below fields, 0 indicates use SOC default

	# PROCHOT_L de-assertion Ramp Time
	register "prochot_l_deassertion_ramp_time_ms" = "20"

	# Lower die temperature limit
	register "thermctl_limit_degreeC" = "100"

	# FP5 Processor Voltage Supply PSI Currents
	register "psi0_current_limit_mA" = "18000"
	register "psi0_soc_current_limit_mA" = "12000"
	register "vddcr_soc_voltage_margin_mV" = "0"
	register "vddcr_vdd_voltage_margin_mV" = "0"

	# VRM Limits
	register "vrm_maximum_current_limit_mA" = "0"
	register "vrm_soc_maximum_current_limit_mA" = "0"
	register "vrm_current_limit_mA" = "0"
	register "vrm_soc_current_limit_mA" = "0"

	# Misc SMU settings
	register "sb_tsi_alert_comparator_mode_en" = "0"
	register "core_dldo_bypass" = "1"
	register "min_soc_vid_offset" = "0"
	register "aclk_dpm0_freq_400MHz" = "0"

	# End : OPN Performance Configuration

	register "emmc_config" = "{
		.timing = SD_EMMC_EMMC_HS400,
		.sdr104_hs400_driver_strength = SD_EMMC_DRIVE_STRENGTH_A,
		/*
		 * The reference design was missing a pull-up on the CMD line.
		 * This means we can't run at the full 400 kHz. By setting this
		 * to 1 we run at the slowest frequency possible by the
		 * controller (~97 kHz).
		 *
		 * Boards that have the pull-up should correctly set this.
		 */
		.init_khz_preset = 1,
	}"

	register "has_usb2_phy_tune_params" = "1"

	# Controller0 Port0 Default
	register "usb_2_port_tune_params[0]" = "{
		.com_pds_tune = 0x07,
		.sq_rx_tune = 0x3,
		.tx_fsls_tune = 0x3,
		.tx_pre_emp_amp_tune = 0x03,
		.tx_pre_emp_pulse_tune = 0x0,
		.tx_rise_tune = 0x1,
		.tx_vref_tune = 0x6,
		.tx_hsxv_tune = 0x3,
		.tx_res_tune = 0x01,
	}"

	# Controller0 Port1 Default
	register "usb_2_port_tune_params[1]" = "{
		.com_pds_tune = 0x07,
		.sq_rx_tune = 0x3,
		.tx_fsls_tune = 0x3,
		.tx_pre_emp_amp_tune = 0x03,
		.tx_pre_emp_pulse_tune = 0x0,
		.tx_rise_tune = 0x1,
		.tx_vref_tune = 0x6,
		.tx_hsxv_tune = 0x3,
		.tx_res_tune = 0x01,
	}"

	# Controller0 Port2 Default
	register "usb_2_port_tune_params[2]" = "{
		.com_pds_tune = 0x07,
		.sq_rx_tune = 0x3,
		.tx_fsls_tune = 0x3,
		.tx_pre_emp_amp_tune = 0x03,
		.tx_pre_emp_pulse_tune = 0x0,
		.tx_rise_tune = 0x1,
		.tx_vref_tune = 0x6,
		.tx_hsxv_tune = 0x3,
		.tx_res_tune = 0x01,
	}"

	# Controller0 Port3 Default
	register "usb_2_port_tune_params[3]" = "{
		.com_pds_tune = 0x07,
		.sq_rx_tune = 0x3,
		.tx_fsls_tune = 0x3,
		.tx_pre_emp_amp_tune = 0x03,
		.tx_pre_emp_pulse_tune = 0x0,
		.tx_rise_tune = 0x1,
		.tx_vref_tune = 0x6,
		.tx_hsxv_tune = 0x3,
		.tx_res_tune = 0x01,
	}"

	# Controller1 Port0 Default
	register "usb_2_port_tune_params[4]" = "{
		.com_pds_tune = 0x07,
		.sq_rx_tune = 0x3,
		.tx_fsls_tune = 0x3,
		.tx_pre_emp_amp_tune = 0x02,
		.tx_pre_emp_pulse_tune = 0x0,
		.tx_rise_tune = 0x1,
		.tx_vref_tune = 0x5,
		.tx_hsxv_tune = 0x3,
		.tx_res_tune = 0x01,
	}"

	# Controller1 Port1 Default
	register "usb_2_port_tune_params[5]" = "{
		.com_pds_tune = 0x07,
		.sq_rx_tune = 0x3,
		.tx_fsls_tune = 0x3,
		.tx_pre_emp_amp_tune = 0x02,
		.tx_pre_emp_pulse_tune = 0x0,
		.tx_rise_tune = 0x1,
		.tx_vref_tune = 0x5,
		.tx_hsxv_tune = 0x3,
		.tx_res_tune = 0x01,
	}"

	# Start RV2 USB3 PHY Parameters
	register "usb3_phy_override" = "0"

	# USB3 Port0 Default
	register "usb3_phy_tune_params[0]" = "{
			.rx_eq_delta_iq_ovrd_val = 0x0,
			.rx_eq_delta_iq_ovrd_en = 0x0,
	}"

	# USB3 Port1 Default
	register "usb3_phy_tune_params[1]" = "{
			.rx_eq_delta_iq_ovrd_val = 0x0,
			.rx_eq_delta_iq_ovrd_en = 0x0,
	}"

	# USB3 Port2 Default
	register "usb3_phy_tune_params[2]" = "{
			.rx_eq_delta_iq_ovrd_val = 0x0,
			.rx_eq_delta_iq_ovrd_en = 0x0,
	}"

	# USB3 Port3 Default
	register "usb3_phy_tune_params[3]" = "{
			.rx_eq_delta_iq_ovrd_val = 0x0,
			.rx_eq_delta_iq_ovrd_en = 0x0,
	}"

	# SUP_DIG_LVL_OVRD_IN Default
	register "usb3_rx_vref_ctrl" = "0x10"
	register "usb3_rx_vref_ctrl_en" = "0x00"
	register "usb_3_tx_vboost_lvl" = "0x07"
	register "usb_3_tx_vboost_lvl_en" = "0x00"

	# SUPX_DIG_LVL_OVRD_IN Default
	register "usb_3_rx_vref_ctrl_x" = "0x10"
	register "usb_3_rx_vref_ctrl_en_x" = "0x00"
	register "usb_3_tx_vboost_lvl_x" = "0x07"
	register "usb_3_tx_vboost_lvl_en_x" = "0x00"

	# End RV2 USB3 phy setting

	# USB OC pin mapping
	register "usb_port_overcurrent_pin[0]" = "USB_OC_PIN_0"	# USB C0
	register "usb_port_overcurrent_pin[1]" = "USB_OC_PIN_1"	# USB C1
	register "usb_port_overcurrent_pin[2]" = "USB_OC_PIN_0"	# USB A0
	register "usb_port_overcurrent_pin[3]" = "USB_OC_PIN_1"	# USB A1
	register "usb_port_overcurrent_pin[4]" = "USB_OC_NONE"	# Camera
	register "usb_port_overcurrent_pin[5]" = "USB_OC_NONE"	# Bluetooth

	# SPI Configuration
	register "common_config.spi_config" = "{
		.normal_speed = SPI_SPEED_33M, /* MHz */
		.fast_speed = SPI_SPEED_66M, /* MHz */
		.altio_speed = SPI_SPEED_66M, /* MHz */
		.tpm_speed = SPI_SPEED_66M, /* MHz */
		.read_mode = SPI_READ_MODE_DUAL122,
	}"

	# eSPI Configuration
	register "common_config.espi_config" = "{
		.std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X60_0X64_EN,
		.generic_io_range[0] = {
			.base = 0x62,
			/*
			 * Only 0x62 and 0x66 are required. But, this is not supported by
			 * standard IO decodes and there are only 4 generic I/O windows
			 * available. Hence, open a window from 0x62-0x67.
			 */
			.size = 5,
		},
		.generic_io_range[1] = {
			.base = 0x800,   /* EC_HOST_CMD_REGION0 */
			.size = 256,     /* EC_HOST_CMD_REGION_SIZE * 2 */
		},
		.generic_io_range[2] = {
			.base = 0x900,   /* EC_LPC_ADDR_MEMMAP */
			.size = 255,     /* EC_MEMMAP_SIZE */
		},
		.generic_io_range[3] = {
			.base = 0x200,   /* EC_LPC_ADDR_HOST_DATA */
			.size = 8,       /* 0x200 - 0x207 */
		},

		.io_mode = ESPI_IO_MODE_QUAD,
		.op_freq_mhz = ESPI_OP_FREQ_33_MHZ,
		.crc_check_enable = 1,
		.alert_pin = ESPI_ALERT_PIN_PUSH_PULL,
		.periph_ch_en = 1,
		.vw_ch_en = 1,
		.oob_ch_en = 0,
		.flash_ch_en = 0,

		.vw_irq_polarity = ESPI_VW_IRQ_LEVEL_HIGH(1) | ESPI_VW_IRQ_LEVEL_HIGH(12),
	}"

	register "i2c_scl_reset" = "GPIO_I2C2_SCL | GPIO_I2C3_SCL"

	# genral purpose PCIe clock output configuration
	register "gpp_clk_config[0]" = "GPP_CLK_REQ" # WLAN
	register "gpp_clk_config[1]" = "GPP_CLK_REQ" # SD Reader
	register "gpp_clk_config[2]" = "GPP_CLK_REQ" # NVME SSD
	register "gpp_clk_config[3]" = "GPP_CLK_OFF"
	register "gpp_clk_config[4]" = "GPP_CLK_OFF"
	register "gpp_clk_config[5]" = "GPP_CLK_OFF"
	register "gpp_clk_config[6]" = "GPP_CLK_OFF"

	register "pspp_policy" = "DXIO_PSPP_POWERSAVE"

	# See AMD 55570-B1 Table 13: PCI Device ID Assignments.
	device domain 0 on
		subsystemid 0x1022 0x1510 inherit
		device ref iommu on end
		device ref gpp_bridge_1 on # Wifi
			chip drivers/wifi/generic
				register "wake" = "GEVENT_8"
				device pci 00.0 on  end
			end
		end
		device ref gpp_bridge_2 on end # SD
		device ref internal_bridge_a on
			device ref gfx on  end # Internal GPU
			device ref gfx_hda on end # Display HDA
			device ref crypto on end # Crypto Coprocessor
			device ref xhci_0 on # USB 3.1
				chip drivers/usb/acpi
					register "desc" = ""Root Hub""
					register "type" = "UPC_TYPE_HUB"
					device usb 0.0 on
						chip drivers/usb/acpi
							register "desc" = ""Left Type-C Port""
							register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
							register "group" = "ACPI_PLD_GROUP(1, 1)"
							device usb 2.0 on end
						end
						chip drivers/usb/acpi
							register "desc" = ""Right Type-C Port""
							register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
							register "group" = "ACPI_PLD_GROUP(2, 2)"
							device usb 2.1 on end
						end
						chip drivers/usb/acpi
							register "desc" = ""Left Type-A Port""
							register "type" = "UPC_TYPE_USB3_A"
							register "group" = "ACPI_PLD_GROUP(1, 2)"
							device usb 2.2 on end
						end
						chip drivers/usb/acpi
							register "desc" = ""Right Type-A Port""
							register "type" = "UPC_TYPE_USB3_A"
							register "group" = "ACPI_PLD_GROUP(2, 1)"
							device usb 2.3 on end
						end
						chip drivers/usb/acpi
							register "desc" = ""User-Facing Camera""
							register "type" = "UPC_TYPE_INTERNAL"
							device usb 2.4 on end
						end
						chip drivers/usb/acpi
							register "desc" = ""Bluetooth""
							register "type" = "UPC_TYPE_INTERNAL"
							register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_143)"
							device usb 2.5 on end
						end
						chip drivers/usb/acpi
							register "desc" = ""Left Type-C Port""
							register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
							register "group" = "ACPI_PLD_GROUP(1, 1)"
							device usb 3.0 on end
						end
						chip drivers/usb/acpi
							register "desc" = ""Right Type-C Port""
							register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
							register "group" = "ACPI_PLD_GROUP(2, 2)"
							device usb 3.1 on end
						end
						chip drivers/usb/acpi
							register "desc" = ""Left Type-A Port""
							register "type" = "UPC_TYPE_USB3_A"
							register "group" = "ACPI_PLD_GROUP(1, 2)"
							device usb 3.2 on end
						end
						chip drivers/usb/acpi
							register "desc" = ""Right Type-A Port""
							register "type" = "UPC_TYPE_USB3_A"
							register "group" = "ACPI_PLD_GROUP(2, 1)"
							device usb 3.3 on end
						end
					end
				end
			end
			device ref acp on
				chip drivers/amd/i2s_machine_dev
					register "hid" = ""AMDI5682""
					# DMIC select GPIO for ACP machine device
					# This GPIO is used to select DMIC0 or DMIC1 by the
					# kernel driver. It does not really have a polarity
					# since low and high control the selection of DMIC and
					# hence does not have an active polarity.
					# Kernel driver does not use the polarity field and
					# instead treats the GPIO selection as follows:
					# Set low (0) = Select DMIC0
					# Set high (1) = Select DMIC1
					register "dmic_select_gpio" = "ACPI_GPIO_OUTPUT(GPIO_67)"
					device generic 0.0 on end
				end
			end # Audio
			device ref hda off end # HDA
			device ref mp2 on end # non-Sensor Fusion Hub device
		end
		device ref lpc_bridge on
			chip ec/google/chromeec
				device pnp 0c09.0 on
					chip ec/google/chromeec/i2c_tunnel
						register "uid" = "1"
						register "remote_bus" = "8"
						device generic 0.0 on
							chip drivers/i2c/generic
								register "hid" = ""10EC5682""
								register "name" = ""RT58""
								register "uid" = "1"
								register "desc" = ""Realtek RT5682""
								register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPIO_84)"
								register "property_count" = "2"
								register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
								register "property_list[0].name" = ""realtek,jd-src""
								register "property_list[0].integer" = "1"
								register "property_list[1].type" = "ACPI_DP_TYPE_STRING"
								register "property_list[1].name" = ""realtek,mclk-name""
								register "property_list[1].string" = ""oscout1""
								device i2c 1a on end
							end
						end
					end
					chip ec/google/chromeec/audio_codec
						register "uid" = "1"
						device generic 0 on end
					end
				end
			end
		end
	end # domain

	device mmio 0xfedc5000 on
		chip drivers/i2c/tpm
			register "hid" = ""GOOG0005""
			register "desc" = ""Cr50 TPM""
			register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_3)"
			device i2c 50 on end
		end
	end

	device mmio 0xfedca000 off end # UART1
	device mmio 0xfedce000 off end # UART2
	device mmio 0xfedcf000 off end # UART3

end	# chip soc/amd/picasso