commit 5ef051a53a03d537b6feab4e85edb69835eb6998
author Lee Leahy <leroy.p.leahy@intel.com> Fri Apr 29 15:16:54 2016 -0700
committer Leroy P Leahy <leroy.p.leahy@intel.com> Tue May 31 21:50:31 2016 +0200
tree eb2c8089bf5fc987f6bafe4587be4db0aef66005
parent a87fcabd2efe49c8035b76146401e190a0ea6593

soc/intel/quark: Add PCIe reset support

Migrate PCIe reset from PlatformPciHelperLib in QuarkFspPkg into
coreboot.

Change-Id: I1c33fa16b0323091e8f9bd503bbfdb8a253a76d4
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14944
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

src/mainboard/intel/galileo/gen1.h

diff --git a/src/mainboard/intel/galileo/gen1.h b/src/mainboard/intel/galileo/gen1.h
index 26335da..e1e8f59 100644
--- a/src/mainboard/intel/galileo/gen1.h
+++ b/src/mainboard/intel/galileo/gen1.h
@@ -13,6 +13,9 @@
  * GNU General Public License for more details.
  */
 
+/* PCIe reset pin */
+#define GEN1_PCI_RESET_RESUMEWELL_GPIO		3
+
 /* Jumper J2 determines the slave address of Cypress I/O GPIO expander */
 #define GALILEO_DETERMINE_IOEXP_SLA_RESUMEWELL_GPIO     5
 

src/mainboard/intel/galileo/gen2.h

diff --git a/src/mainboard/intel/galileo/gen2.h b/src/mainboard/intel/galileo/gen2.h
index 108971b..8eee744 100644
--- a/src/mainboard/intel/galileo/gen2.h
+++ b/src/mainboard/intel/galileo/gen2.h
@@ -13,6 +13,9 @@
  * GNU General Public License for more details.
  */
 
+/* PCIe reset pin */
+#define GEN2_PCI_RESET_RESUMEWELL_GPIO		0
+
 static const struct reg_script gen2_gpio_init[] = {
 	/* Initialize the legacy GPIO controller */
 	REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGEN_CORE_WELL, 0x03),

src/mainboard/intel/galileo/gpio.c

diff --git a/src/mainboard/intel/galileo/gpio.c b/src/mainboard/intel/galileo/gpio.c
index a411c5a..3184381 100644
--- a/src/mainboard/intel/galileo/gpio.c
+++ b/src/mainboard/intel/galileo/gpio.c
@@ -50,3 +50,20 @@
 		script = gen1_gpio_init;
 	reg_script_run(script);
 }
+
+void mainboard_gpio_pcie_reset(uint32_t pin_value)
+{
+	uint32_t pin_number;
+	uint32_t value;
+
+	/* Determine the correct PCIe reset pin */
+	if (IS_ENABLED(CONFIG_GALILEO_GEN2))
+		pin_number = GEN2_PCI_RESET_RESUMEWELL_GPIO;
+	else
+		pin_number = GEN1_PCI_RESET_RESUMEWELL_GPIO;
+
+	/* Update the PCIe reset value */
+	value = reg_legacy_gpio_read(R_QNC_GPIO_RGLVL_RESUME_WELL);
+	value = (value & ~(1 << pin_number)) | ((pin_value & 1) << pin_number);
+	reg_legacy_gpio_write(R_QNC_GPIO_RGLVL_RESUME_WELL, value);
+}