commit | 5edbb1c5d917ae27aa8c869a92f3f8750dea9845 | [log] [tgz] |
---|---|---|
author | Furquan Shaikh <furquan@google.com> | Mon Jun 15 17:22:02 2020 -0700 |
committer | Furquan Shaikh <furquan@google.com> | Wed Jun 17 20:54:32 2020 +0000 |
tree | 6d4a891ced5ea77980a865b1e6b89ec6a8fb3f15 | |
parent | 3cd3cb6f33cbbd18f9acac01ca5008e2dfb76242 [diff] |
Revert "soc/amd/picasso: Reconfigure SPI speeds after FSP-S has run" This reverts commit d5f1e0f9734273f79ebd313bb6a17eda04c22c11. Reason for revert: FSP-S is now fixed to not touch the SPI configuration registers. Thus, coreboot does not need to reconfigure SPI after FSP-S has run. BUG=b:153506142 TEST=Verified that SPI configuration registers look the same before and after FSP-S has run. em100 works fine without any additional changes in coreboot to reconfigure SPI. Change-Id: I4832e62e0331aa39abe0cca7725915262bb2cf83 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin Frodsham <justin.frodsham@amd.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAIN
Kconfig option if you're feeling lucky (no support in this case).Optional:
make menuconfig
and make nconfig
)Please consult https://www.coreboot.org/Build_HOWTO for details.
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.