commit 5e9afe7272d110265ffa6f5465fa942c2bf4961f
author Felix Held <felix-coreboot@felixheld.de> Thu Apr 20 12:55:55 2023 +0200
committer Felix Held <felix-coreboot@felixheld.de> Fri Apr 21 15:10:18 2023 +0000
tree d73229f9cf598cd940c6746cd7dc7e88039dcb42
parent df2edde891dc6df4113c2d720d70eabe8c888139

include/cpu/amd/mtrr: rename functions to get top of memory regions

Rename amd_topmem and amd_topmem2 to get_top_of_mem_below_4gb and
get_top_of_mem_above_4g to make it clearer what those functions return.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic6e98d94c731af74aea0ce276a9a7e4867e3986f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>

src/cpu/amd/mtrr/amd_mtrr.c

diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c
index 405e92a..f904df9 100644
--- a/src/cpu/amd/mtrr/amd_mtrr.c
+++ b/src/cpu/amd/mtrr/amd_mtrr.c
@@ -7,7 +7,7 @@
 
 void add_uma_resource_below_tolm(struct device *nb, int idx)
 {
-	uint32_t topmem = amd_topmem();
+	uint32_t topmem = get_top_of_mem_below_4gb();
 	uint32_t top_of_cacheable = restore_top_of_low_cacheable();
 
 	if (top_of_cacheable == topmem)

src/include/cpu/amd/mtrr.h

diff --git a/src/include/cpu/amd/mtrr.h b/src/include/cpu/amd/mtrr.h
index f1b95b6..b8b820c 100644
--- a/src/include/cpu/amd/mtrr.h
+++ b/src/include/cpu/amd/mtrr.h
@@ -65,12 +65,12 @@
 		);
 }
 
-static inline uint64_t amd_topmem(void)
+static inline uint64_t get_top_of_mem_below_4gb(void)
 {
 	return rdmsr(TOP_MEM).lo;
 }
 
-static inline uint64_t amd_topmem2(void)
+static inline uint64_t get_top_of_mem_above_4g(void)
 {
 	msr_t msr = rdmsr(TOP_MEM2);
 	return (uint64_t)msr.hi << 32 | msr.lo;

src/northbridge/amd/pi/00730F01/northbridge.c

diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c
index 5f3b4d9..d963171 100644
--- a/src/northbridge/amd/pi/00730F01/northbridge.c
+++ b/src/northbridge/amd/pi/00730F01/northbridge.c
@@ -781,7 +781,7 @@
 	pci_domain_read_resources(dev);
 
 	/* TOP_MEM MSR is our boundary between DRAM and MMIO under 4G */
-	mmio_basek = amd_topmem() >> 10;
+	mmio_basek = get_top_of_mem_below_4gb() >> 10;
 
 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
 	/* if the hw mem hole is already set in raminit stage, here we will compare
@@ -837,7 +837,7 @@
 				sizek = 0;
 			}
 			else {
-				uint64_t topmem2 = amd_topmem2();
+				uint64_t topmem2 = get_top_of_mem_above_4g();
 				basek = 4 * 1024 * 1024;
 				sizek = topmem2 / 1024 - basek;
 			}

src/soc/amd/stoneyridge/northbridge.c

diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c
index 068ba56..ccfa9cb 100644
--- a/src/soc/amd/stoneyridge/northbridge.c
+++ b/src/soc/amd/stoneyridge/northbridge.c
@@ -276,7 +276,7 @@
  */
 void amd_initcpuio(void)
 {
-	uintptr_t topmem = amd_topmem();
+	uintptr_t topmem = get_top_of_mem_below_4gb();
 	uintptr_t base, limit;
 
 	/* Enable legacy video routing: D18F1xF4 VGA Enable */