src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/XhciMid.c

/* $NoKeywords:$ */
/**
 * @file
 *
 * Config Fch USB3 controller
 *
 * Init USB3 features.
 *
 * @xrefitem bom "File Content Label" "Release Content"
 * @e project:     AGESA
 * @e sub-project: FCH
 * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
 *
 */
/*;********************************************************************************
;
 * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *     * Redistributions of source code must retain the above copyright
 *       notice, this list of conditions and the following disclaimer.
 *     * Redistributions in binary form must reproduce the above copyright
 *       notice, this list of conditions and the following disclaimer in the
 *       documentation and/or other materials provided with the distribution.
 *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
 *       its contributors may be used to endorse or promote products derived
 *       from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;*********************************************************************************/
#include "FchPlatform.h"
#include "Filecode.h"
#define FILECODE PROC_FCH_USB_XHCIMID_FILECODE

/**
 * FchInitMidUsbXhci - Config USB3 controller after PCI
 * emulation
 *
 *
 *
 * @param[in] FchDataPtr Fch configuration structure pointer.
 *
 */
VOID
FchInitMidUsbXhci (
  IN  VOID     *FchDataPtr
  )
{
  FCH_DATA_BLOCK   *LocalCfgPtr;

  LocalCfgPtr = (FCH_DATA_BLOCK *)FchDataPtr;
  if ( LocalCfgPtr->Usb.Xhci0Enable == TRUE ) {
    RwPci ((USB_XHCI_BUS_DEV_FUN << 16) + FCH_XHCI_REG04, AccessWidth8, 0, BIT1, ((FCH_DATA_BLOCK *)FchDataPtr)->StdHeader);
    if (((FCH_DATA_BLOCK *)FchDataPtr)->Usb.XhciSsid != 0 ) {
      RwPci ((USB_XHCI_BUS_DEV_FUN << 16) + FCH_XHCI_REG2C, AccessWidth32, 0x00, ((FCH_DATA_BLOCK *)FchDataPtr)->Usb.XhciSsid, ((FCH_DATA_BLOCK *)FchDataPtr)->StdHeader);
    }
  }

  if ( LocalCfgPtr->Usb.Xhci1Enable == TRUE ) {
    RwPci ((USB_XHCI1_BUS_DEV_FUN << 16) + FCH_XHCI_REG04, AccessWidth8, 0, BIT1, ((FCH_DATA_BLOCK *)FchDataPtr)->StdHeader);
    if (((FCH_DATA_BLOCK *)FchDataPtr)->Usb.XhciSsid != 0 ) {
      RwPci ((USB_XHCI1_BUS_DEV_FUN << 16) + FCH_XHCI_REG2C, AccessWidth32, 0x00, ((FCH_DATA_BLOCK *)FchDataPtr)->Usb.XhciSsid, ((FCH_DATA_BLOCK *)FchDataPtr)->StdHeader);
    }
    //
    // Block Write to DID & SID to pass DTM
    //
    RwXhciIndReg (FCH_XHCI_IND_REG04, (UINT32)~BIT8, (UINT32)BIT8, ((FCH_DATA_BLOCK *)FchDataPtr)->StdHeader);
  }
}