soc/intel/tigerlake: Generate LP4x SPD files using gen_spd.go
This change uses gen_spd.go and global_lp4x_mem_parts.json.txt to
generate SPD files for currently known LP4x memory parts that can be
used with TGL-based mainboards.
Following files are added:
1. spd-*.hex: SPD files auto-generated by gen_spd.go
2. spd_manifest.generated.txt: Manifest file auto-generated by
gen_spd.go
Mainboards can use the SPD files from SoC directly when creating SPD
binary to add to CBFS.
BUG=b:147321551,b:155239397
Change-Id: Ic3935e4f6d106cbdf496fdfa28a0991e2d238fd9
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41875
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
diff --git a/src/soc/intel/tigerlake/spd/lp4x/spd-1.hex b/src/soc/intel/tigerlake/spd/lp4x/spd-1.hex
new file mode 100644
index 0000000..55d327a
--- /dev/null
+++ b/src/soc/intel/tigerlake/spd/lp4x/spd-1.hex
@@ -0,0 +1,32 @@
+23 11 11 0E 15 21 94 08 00 00 00 00 02 01 00 00
+00 00 04 FF 92 54 05 00 87 00 90 A8 90 C0 08 60
+04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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diff --git a/src/soc/intel/tigerlake/spd/lp4x/spd-2.hex b/src/soc/intel/tigerlake/spd/lp4x/spd-2.hex
new file mode 100644
index 0000000..1558f50
--- /dev/null
+++ b/src/soc/intel/tigerlake/spd/lp4x/spd-2.hex
@@ -0,0 +1,32 @@
+23 11 11 0E 16 29 B8 08 00 00 00 00 09 01 00 00
+00 00 04 FF 12 29 15 00 96 00 90 A8 90 C0 08 60
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diff --git a/src/soc/intel/tigerlake/spd/lp4x/spd-3.hex b/src/soc/intel/tigerlake/spd/lp4x/spd-3.hex
new file mode 100644
index 0000000..c4fd994
--- /dev/null
+++ b/src/soc/intel/tigerlake/spd/lp4x/spd-3.hex
@@ -0,0 +1,32 @@
+23 11 11 0E 15 21 B4 08 00 00 00 00 0A 01 00 00
+00 00 04 FF 92 54 05 00 87 00 90 A8 90 C0 08 60
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+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/soc/intel/tigerlake/spd/lp4x/spd-4.hex b/src/soc/intel/tigerlake/spd/lp4x/spd-4.hex
new file mode 100644
index 0000000..4988cb4
--- /dev/null
+++ b/src/soc/intel/tigerlake/spd/lp4x/spd-4.hex
@@ -0,0 +1,32 @@
+23 11 11 0E 16 29 94 08 00 00 00 00 02 01 00 00
+00 00 04 FF 92 54 05 00 87 00 90 A8 90 E0 0B F0
+05 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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diff --git a/src/soc/intel/tigerlake/spd/lp4x/spd-5.hex b/src/soc/intel/tigerlake/spd/lp4x/spd-5.hex
new file mode 100644
index 0000000..9f5bb03
--- /dev/null
+++ b/src/soc/intel/tigerlake/spd/lp4x/spd-5.hex
@@ -0,0 +1,32 @@
+23 11 11 0E 14 19 94 08 00 00 00 00 02 01 00 00
+00 00 05 0A 80 54 01 00 89 00 90 A8 90 A0 05 D0
+02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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diff --git a/src/soc/intel/tigerlake/spd/lp4x/spd_manifest.generated.txt b/src/soc/intel/tigerlake/spd/lp4x/spd_manifest.generated.txt
new file mode 100644
index 0000000..d11e93d
--- /dev/null
+++ b/src/soc/intel/tigerlake/spd/lp4x/spd_manifest.generated.txt
@@ -0,0 +1,9 @@
+H9HCNNNBKMMLXR-NEE,spd-1.hex
+H9HCNNNFAMMLXR-NEE,spd-2.hex
+K4U6E3S4AA-MGCL,spd-1.hex
+K4UBE3D4AA-MGCL,spd-3.hex
+MT53E1G32D2NP-046 WT:A,spd-4.hex
+H9HKNNNCRMBVAR-NEH,spd-1.hex
+MT53E1G64D4SQ-046 WT:A,spd-4.hex
+MT53E512M32D2NP-046 WT:F,spd-1.hex
+NT6AP256T32AV-J2,spd-5.hex