tree 58f9446c2fe2ea890e658454bb61e18f27376042
parent 6fb87c2b7705f8266a4468740c31c1a372c9da88
author Eric Lai <ericr_lai@compal.corp-partner.google.com> 1607158183 +0800
committer Patrick Georgi <pgeorgi@google.com> 1612517998 +0000

soc/intel/alderlake: Refactor PCIE port config

Refactor PCIE port config structure. Make it easier to map from
schematic. We don't have to convert the PCIE ports RP number and
CLK source in devicetree. All the convert will be done by SoC level.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>