vendorcode/intel: Update FSP Header files per v2.0.0

Update FSP header files to match GLK FSP Reference Code Release v2.0.0

Change-Id: I93d95e1977a4e31981e8b91882059611d91f78a5
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-on: https://review.coreboot.org/25247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
diff --git a/src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h
index acbc596..4559e22 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h
@@ -1,6 +1,6 @@
 /** @file
 
-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
 
 Redistribution and use in source and binary forms, with or without modification,
 are permitted provided that the following conditions are met:
@@ -52,6 +52,9 @@
 #define MAX_SPD_SAVE 29
 #endif
 
+#define MRC_DDR_TYPE_LPDDR4   6
+#define MRC_DDR_TYPE_DDR4     7
+
 //
 // MRC version description.
 //
@@ -805,11 +808,9 @@
 **/
   UINT32                      OemLoadingBase;
 
-/** Offset 0x0120 - OEM File Name to Load
-  Specify a file name to load from CSE file system after memory is available. Empty
-  indicates no file needs to be loaded.
+/** Offset 0x0120
 **/
-  UINT8                       OemFileName[16];
+  UINT8                       Reserved[16];
 
 /** Offset 0x0130
 **/
@@ -962,37 +963,41 @@
 **/
   VOID*                       VariableNvsBufferPtr;
 
-/** Offset 0x0164
+/** Offset 0x0164 - PERST pin for RootPort 0
+  Address for PERST pin for Rootport 0. For Intel RVP, address of N_GPIO_105. 0x00C507D0(Default).
+**/
+  UINT32                      RootPort0Perst;
+
+/** Offset 0x0168 - PERST pin for RootPort 1
+  Address for PERST pin for Rootport 1. For Intel RVP, address of  A_GPIO_163. 0x00C90670(Default).
+**/
+  UINT32                      RootPort1Perst;
+
+/** Offset 0x016C - PERST pin for RootPort 2
+  Address for PERST pin for Rootport 2. For Intel RVP, address of N_GPIO_137. 0x00C509D0(Default).
+**/
+  UINT32                      RootPort2Perst;
+
+/** Offset 0x0170 - PERST pin for RootPort 3
+  Address for PERST pin for Rootport 3.
+**/
+  UINT32                      RootPort3Perst;
+
+/** Offset 0x0174 - PERST pin for RootPort 4
+  Address for PERST pin for Rootport 4. For Intel RVP, address of  SCC_GPIO_210. 0x00C806D0(Default).
+**/
+  UINT32                      RootPort4Perst;
+
+/** Offset 0x0178 - PERST pin for RootPort 5
+  Address for PERST pin for Rootport 5.
+**/
+  UINT32                      RootPort5Perst;
+
+/** Offset 0x017C
 **/
   UINT8                       ReservedFspmUpd[4];
 } FSP_M_CONFIG;
 
-/** Fsp M Test Configuration
-**/
-typedef struct {
-
-/** Offset 0x0168
-**/
-  UINT32                      Signature;
-
-/** Offset 0x016C
-**/
-  UINT8                       ReservedFspmTestUpd[20];
-} FSP_M_TEST_CONFIG;
-
-/** Fsp M Restricted Configuration
-**/
-typedef struct {
-
-/** Offset 0x0180
-**/
-  UINT32                      Signature;
-
-/** Offset 0x0184
-**/
-  UINT8                       ReservedFspmRestrictedUpd[124];
-} FSP_M_RESTRICTED_CONFIG;
-
 /** Fsp M UPD Configuration
 **/
 typedef struct {
@@ -1009,17 +1014,9 @@
 **/
   FSP_M_CONFIG                FspmConfig;
 
-/** Offset 0x0168
-**/
-  FSP_M_TEST_CONFIG           FspmTestConfig;
-
 /** Offset 0x0180
 **/
-  FSP_M_RESTRICTED_CONFIG     FspmRestrictedConfig;
-
-/** Offset 0x0200
-**/
-  UINT8                       UnusedUpdSpace1[6];
+  UINT8                       UnusedUpdSpace1[134];
 
 /** Offset 0x0206
 **/
diff --git a/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h
index e4839e0..cc50058 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h
@@ -1,6 +1,6 @@
 /** @file
 
-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
 
 Redistribution and use in source and binary forms, with or without modification,
 are permitted provided that the following conditions are met:
@@ -1672,74 +1672,40 @@
 **/
   UINT16                      HgSubSystemId;
 
-/** Offset 0x0388
+/** Offset 0x0388 - USB Per Port HS Preemphasis Bias
+  USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-40.5mV, 010b-60.5mV, 011b-102mV,
+  100b-102mV, 101b-142mV, 110b-162.5mV, 111b-202.5mV. One byte for each port.
 **/
-  UINT8                       ReservedFspsUpd[8];
+  UINT8                       Usb2AfePetxiset[8];
+
+/** Offset 0x0390 - USB Per Port HS Transmitter Bias
+  USB Per Port HS Transmitter Bias. 000b-0mV, 001b-40.5mV, 010b-60.5mV, 011b-102mV,
+  100b-102mV, 101b-142mV, 110b-162.5mV, 111b-202.5mV. One byte for each port.
+**/
+  UINT8                       Usb2AfeTxiset[8];
+
+/** Offset 0x0398 - USB Per Port HS Transmitter Emphasis
+  USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON,
+  10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port.
+**/
+  UINT8                       Usb2AfePredeemp[8];
+
+/** Offset 0x03A0 - USB Per Port Half Bit Pre-emphasis
+  USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis.
+  One byte for each port.
+**/
+  UINT8                       Usb2AfePehalfbit[8];
+
+/** Offset 0x03A8 - Intel Processor Trace output Scheme method
+  Intel Processor Trace output Scheme method 0:Single Range Output (Default) 1. ToPA Output
+**/
+  UINT8                       ProcessorTraceOutputScheme;
+
+/** Offset 0x03A9
+**/
+  UINT8                       ReservedFspsUpd[7];
 } FSP_S_CONFIG;
 
-/** Fsp S Test Configuration
-**/
-typedef struct {
-
-/** Offset 0x0390
-**/
-  UINT32                      Signature;
-
-/** Offset 0x0394
-**/
-  UINT8                       ReservedFspsTestUpd[12];
-} FSP_S_TEST_CONFIG;
-
-/** Fsp S Restricted Configuration
-**/
-typedef struct {
-
-/** Offset 0x03A0
-**/
-  UINT32                      Signature;
-
-/** Offset 0x03A4 - Selective enable SGX
-  Selective enable SGX. 0xFFFF(Default).
-**/
-  UINT16                      SelectiveEnableSgx;
-
-/** Offset 0x03A6 - SGX debug mode
-  Select SGX mode. 0:Disable(default), 1:Enable
-  0:Disable(default), 1:Enable
-**/
-  UINT8                       SgxDebugMode;
-
-/** Offset 0x03A7 - SGX Launch Control Policy Mode
-  Select Launch Control Policy Mode. 0:Intel - Default, 1:Per-boot Select mode(default)
-  0:Intel locked , 1:Unlocked mode(default) , 2: Locked mode
-**/
-  UINT8                       SgxLcp;
-
-/** Offset 0x03A8 - LE KeyHash0
-  LE KeyHash0. 0x0(Default).
-**/
-  UINT64                      SgxLePubKeyHash0;
-
-/** Offset 0x03B0 - LE KeyHash1
-  LE KeyHash1. 0x0(Default).
-**/
-  UINT64                      SgxLePubKeyHash1;
-
-/** Offset 0x03B8 - LE KeyHash2
-  LE KeyHash2. 0x0(Default).
-**/
-  UINT64                      SgxLePubKeyHash2;
-
-/** Offset 0x03C0 - LE KeyHash3
-  LE KeyHash3. 0x0(Default).
-**/
-  UINT64                      SgxLePubKeyHash3;
-
-/** Offset 0x03C8
-**/
-  UINT8                       ReservedFspsRestrictedUpd[8];
-} FSP_S_RESTRICTED_CONFIG;
-
 /** Fsp S UPD Configuration
 **/
 typedef struct {
@@ -1752,19 +1718,11 @@
 **/
   FSP_S_CONFIG                FspsConfig;
 
-/** Offset 0x0390
+/** Offset 0x03B0
 **/
-  FSP_S_TEST_CONFIG           FspsTestConfig;
+  UINT8                       UnusedUpdSpace7[78];
 
-/** Offset 0x03A0
-**/
-  FSP_S_RESTRICTED_CONFIG     FspsRestrictedConfig;
-
-/** Offset 0x03D0
-**/
-  UINT8                       UnusedUpdSpace7[6];
-
-/** Offset 0x03D6
+/** Offset 0x03FE
 **/
   UINT16                      UpdTerminator;
 } FSPS_UPD;