This patch adds VGA and PS/2 Keyboard/mouse support to the already existing intel truxton (ep80579) dev board.
This patch tries to improve the pcie portA configuration.
The Matrox G550e PCIe gfx card shipped along with the dev board is supported.

Signed-off-by: Arnaud Maye <arnaud.maye@4dsp.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4615 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
diff --git a/src/mainboard/intel/truxton/Config.lb b/src/mainboard/intel/truxton/Config.lb
index 7ec2da8..a297da1 100644
--- a/src/mainboard/intel/truxton/Config.lb
+++ b/src/mainboard/intel/truxton/Config.lb
@@ -143,6 +143,19 @@
                                                  io 0x60 = 0x2f8
                                                 irq 0x70 = 3
                                         end
+				end
+				chip superio/smsc/smscsuperio
+					device pnp 2e.0 off end
+					device pnp 2e.3 off end
+					device pnp 2e.4 off end
+					device pnp 2e.5 off end
+					device pnp 2e.7 on # PS/2 keyboard / mouse
+            					io 0x60 = 0x60
+            					io 0x62 = 0x64
+            					irq 0x70 = 1	# PS/2 keyboard interrupt
+            					irq 0x72 = 12	# PS/2 mouse interrupt
+					end
+					device pnp 2e.a off end
                                 end
                         end
                         device pci 1f.2 on end  # SATA
diff --git a/src/mainboard/intel/truxton/Options.lb b/src/mainboard/intel/truxton/Options.lb
index 2f98066..2dd7db5 100644
--- a/src/mainboard/intel/truxton/Options.lb
+++ b/src/mainboard/intel/truxton/Options.lb
@@ -37,6 +37,7 @@
 uses CONFIG_ROM_PAYLOAD
 uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
+uses CONFIG_LB_MEM_TOPK
 uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_XIP_ROM_SIZE
@@ -67,6 +68,7 @@
 uses HOSTCC
 uses CONFIG_CROSS_COMPILE
 uses CONFIG_OBJCOPY
+uses CONFIG_CONSOLE_VGA
 
 
 ###
@@ -155,7 +157,12 @@
 ##
 ## coreboot C code runs at this location in RAM
 ##
-default CONFIG_RAMBASE=0x00004000
+default CONFIG_RAMBASE=0x00100000
+
+##
+## in order to have coreboot running at 0x100000, TOPK has to be set
+##
+default CONFIG_LB_MEM_TOPK = 2*1024*1024
 
 ##
 ## Load the payload from the ROM
@@ -202,6 +209,9 @@
 # This defaults to 8 data bits, 1 stop bit, and no parity
 default CONFIG_TTYS0_LCS=0x3
 
+# Enable the VGA console.
+default CONFIG_CONSOLE_VGA=1
+
 ##
 ### Select the coreboot loglevel
 ##
diff --git a/src/mainboard/intel/truxton/devicetree.cb b/src/mainboard/intel/truxton/devicetree.cb
index 7604bea..a21c2f4 100644
--- a/src/mainboard/intel/truxton/devicetree.cb
+++ b/src/mainboard/intel/truxton/devicetree.cb
@@ -26,6 +26,19 @@
                                                  io 0x60 = 0x2f8
                                                 irq 0x70 = 3
                                         end
+				end
+				chip superio/smsc/smscsuperio
+					device pnp 2e.0 off end
+					device pnp 2e.3 off end
+					device pnp 2e.4 off end
+					device pnp 2e.5 off end
+					device pnp 2e.7 on # PS/2 keyboard / mouse
+            					io 0x60 = 0x60
+            					io 0x62 = 0x64
+            					irq 0x70 = 1	# PS/2 keyboard interrupt
+            					irq 0x72 = 12	# PS/2 mouse interrupt
+					end
+					device pnp 2e.a off end
                                 end
                         end
                         device pci 1f.2 on end  # SATA
diff --git a/src/northbridge/intel/i3100/Config.lb b/src/northbridge/intel/i3100/Config.lb
index 6d0fa6f..ac100c5 100644
--- a/src/northbridge/intel/i3100/Config.lb
+++ b/src/northbridge/intel/i3100/Config.lb
@@ -23,5 +23,6 @@
 
 driver northbridge.o
 driver pciexp_porta.o
+driver pciexp_porta_ep80579.o
 
 default CONFIG_HAVE_HIGH_TABLES=1
diff --git a/src/northbridge/intel/i3100/pciexp_porta_ep80579.c b/src/northbridge/intel/i3100/pciexp_porta_ep80579.c
new file mode 100644
index 0000000..9fbd539
--- /dev/null
+++ b/src/northbridge/intel/i3100/pciexp_porta_ep80579.c
@@ -0,0 +1,112 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 4DSP Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ *
+ */
+
+/* This code is based on src/northbridge/intel/i3100/pciexp_porta.c */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <device/pciexp.h>
+#include <arch/io.h>
+#include "chip.h"
+#include <part/hard_reset.h>
+
+typedef struct northbridge_intel_i3100_config config_t;
+
+static void pcie_init(struct device *dev)
+{
+	config_t *config;
+ 	u16 val;
+
+	/* Get the chip configuration */
+	config = dev->chip_info;
+
+	if(config->intrline) {
+		pci_write_config32(dev, 0x3c, config->intrline);
+	}
+
+	printk_spew("configure PCIe port as \"Slot Implemented\"\n");
+	val = pci_read_config16(dev, 0x66);
+	val &= ~(1<<8);
+	val |= 1<<8;
+	pci_write_config16(dev, 0x66, val);
+
+	/* Todo configure the PCIe bootstrap mode (covered by Intel NDA) */
+}
+
+
+static void pcie_bus_enable_resources(struct device *dev)
+{
+	u8 val8;
+	if (dev->link[0].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
+		printk_spew("Enable VGA IO/MEM forwarding on PCIe port\n");
+		pci_write_config8(dev, PCI_BRIDGE_CONTROL, 8);
+		
+		dev->command |= PCI_COMMAND_IO;
+		dev->command |= PCI_COMMAND_MEMORY;
+	}
+	pci_dev_enable_resources(dev);
+	enable_childrens_resources(dev);
+}
+
+
+static unsigned int pcie_scan_bridge(struct device *dev, unsigned int max)
+{
+	u16 val;
+	u16 ctl;
+	int flag = 0;
+	do {
+		val = pci_read_config16(dev, 0x76);
+		printk_debug("pcie porta 0x76: %02x\n", val);
+		if ((val & (1<<11)) && (!flag)) { /* training error */
+			ctl = pci_read_config16(dev, 0x74);
+			pci_write_config16(dev, 0x74, (ctl | (1<<5)));
+			val = pci_read_config16(dev, 0x76);
+			printk_debug("pcie porta reset 0x76: %02x\n", val);
+			flag=1;
+			hard_reset();
+		}
+	} while	(val & (3<<10));
+	return pciexp_scan_bridge(dev, max);
+}
+
+static struct device_operations pcie_ops  = {
+	.read_resources   = pci_bus_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pcie_bus_enable_resources,
+	.init             = pcie_init,
+	.scan_bus         = pcie_scan_bridge,
+	.reset_bus        = pci_bus_reset,
+	.ops_pci          = 0,
+};
+
+static struct pci_driver pci_driver_0 __pci_driver = {
+	.ops    = &pcie_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_EP80579_PCIE_PA0,
+};
+
+static struct pci_driver pci_driver_1 __pci_driver = {
+	.ops    = &pcie_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_EP80579_PCIE_PA1,
+};
diff --git a/src/northbridge/intel/i3100/raminit_ep80579.c b/src/northbridge/intel/i3100/raminit_ep80579.c
index c871856..5e51361 100644
--- a/src/northbridge/intel/i3100/raminit_ep80579.c
+++ b/src/northbridge/intel/i3100/raminit_ep80579.c
@@ -31,7 +31,7 @@
 {
 	static const u32 register_values[] = {
 		PCI_ADDR(0, 0x00, 0, CKDIS), 0xffff0000, 0x0000ffff,
-		PCI_ADDR(0, 0x00, 0, DEVPRES), 0x00000000, 0x07420801 | DEVPRES_CONFIG,
+		PCI_ADDR(0, 0x00, 0, DEVPRES), 0x00000000, 0x07420001 | DEVPRES_CONFIG,
 		PCI_ADDR(0, 0x00, 0, PAM-1), 0xcccccc7f, 0x33333000,
 		PCI_ADDR(0, 0x00, 0, PAM+3), 0xcccccccc, 0x33333333,
 		PCI_ADDR(0, 0x00, 0, DEVPRES1), 0xffffffff, 0x0040003a,
diff --git a/src/southbridge/intel/i3100/i3100_early_lpc.c b/src/southbridge/intel/i3100/i3100_early_lpc.c
index 97d2b7c..3397aff 100644
--- a/src/southbridge/intel/i3100/i3100_early_lpc.c
+++ b/src/southbridge/intel/i3100/i3100_early_lpc.c
@@ -25,6 +25,9 @@
 	/* Enable decoding of I/O locations for SuperIO devices */
 	pci_write_config16(dev, 0x80, 0x0010);
 	pci_write_config16(dev, 0x82, 0x340f);
+
+	/* Enable the SERIRQs (start pulse width is 8 clock cycles) */
+	pci_write_config8(dev, 0x64, 0xD2);
 }
 
 static void i3100_halt_tco_timer(void)
diff --git a/src/superio/smsc/smscsuperio/superio.c b/src/superio/smsc/smscsuperio/superio.c
index 148eeab..2c20a09 100644
--- a/src/superio/smsc/smscsuperio/superio.c
+++ b/src/superio/smsc/smscsuperio/superio.c
@@ -60,6 +60,7 @@
 #define DME1737		0x78
 #define SCH3112		0x7c
 #define SCH5307		0x81	/* Rebranded LPC47B397(?) */
+#define SCH5027D	0x89
 
 /* Register defines */
 #define DEVICE_ID_REG	0x20	/* Device ID register */
@@ -135,6 +136,7 @@
 	{DME1737,  {0, 3, 4,  5, -1,  7, -1,  -1, -1,  -1, -1, -1, 10, -1, -1}},
 	{SCH3112,  {0, 3, 4,  5, -1,  7, -1,  -1, -1,  -1, -1, -1, 10, -1, -1}},
 	{SCH5307,  {0, 3, 4,  5, -1,  7, -1,  -1,  8,  -1, -1, -1, 10, -1, -1}},
+	{SCH5027D, {0, 3, 4,  5, -1,  7, -1,  -1, -1,  -1, -1, -1, 10, -1, 11}},
 };
 
 /**
diff --git a/targets/intel/truxton/Config.lb b/targets/intel/truxton/Config.lb
index 08c4f73..fd6a7bd 100644
--- a/targets/intel/truxton/Config.lb
+++ b/targets/intel/truxton/Config.lb
@@ -34,7 +34,7 @@
 
 romimage "fallback"
 	option CONFIG_USE_FALLBACK_IMAGE=1
-	payload /tmp/filo.elf
+	payload /tmp/seabios.elf
 end
 
 buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"