soc/amd/cezanne/fsp_m_params: Configure the s0i3_enable UPD
Configure the S0i3 enable UPD based on the mainboard configuration.
BUG=b:178728116
TEST=Build and boot to OS in Guybrush. Enter S0i3 after passing the
sleep state configuration from the mainboard.
Change-Id: I18f43e964d1c70317155394257a5e2c1900816bb
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52618
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
diff --git a/src/soc/amd/cezanne/fsp_m_params.c b/src/soc/amd/cezanne/fsp_m_params.c
index 9d4159d..a83b8b2 100644
--- a/src/soc/amd/cezanne/fsp_m_params.c
+++ b/src/soc/amd/cezanne/fsp_m_params.c
@@ -113,5 +113,8 @@
mcfg->cppc_epp_min_range = config->cppc_epp_min_range;
mcfg->cppc_preferred_cores = config->cppc_preferred_cores;
+ /* S0i3 enable */
+ mcfg->s0i3_enable = config->s0ix_enable;
+
fsp_fill_pcie_ddi_descriptors(mcfg);
}