tree 2e3b37072907c6683f732f22ecfe8f50bebed378
parent 533fc4dfb155bb45e8da279e1b85b676e3f6c58c
author Raul E Rangel <rrangel@chromium.org> 1627080198 -0600
committer Patrick Georgi <pgeorgi@google.com> 1636022032 +0000

commonlib/mem_pool: Allow configuring the alignment

AMD platforms require the destination to be 64 byte aligned in order to
use the SPI DMA controller. This is enforced by the destination address
register because the first 6 bits are marked as reserved.

This change adds an option to the mem_pool so the alignment can be
configured.

BUG=b:179699789
TEST=Boot guybrush to OS

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I8d77ffe4411f86c54450305320c9f52ab41a3075
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56580
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>