| commit | 5ac723e5a4a22bc9a08098cd59de5026b18d362d | [log] [tgz] |
|---|---|---|
| author | Elyes HAOUAS <ehaouas@noos.fr> | Wed Apr 29 09:09:12 2020 +0200 |
| committer | Patrick Georgi <pgeorgi@google.com> | Tue May 26 15:11:33 2020 +0000 |
| tree | 1dd12f2f9c99d90dddfb08da50d7cf46264fc716 | |
| parent | b30fe36734df3c48ec35438052ee8b28bf7a6a44 [diff] [blame] |
nb/intel: Fix 16-bit read/write PCI_COMMAND register Change-Id: I7c7fb10308a6fcd1ead292c53ed03ddc693f6f15 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c index 83bc60e..856eab3 100644 --- a/src/northbridge/intel/pineview/northbridge.c +++ b/src/northbridge/intel/pineview/northbridge.c
@@ -147,12 +147,8 @@ static void mch_domain_init(struct device *dev) { - u32 reg32; - /* Enable SERR */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_SERR; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR); } static const char *northbridge_acpi_name(const struct device *dev)