nb/intel/x4x: Work around a quirk
It looks like this hardware has a bug where the display controller
does not work properly when dram is clocked 533MHz and the channels
are configured in non-stacked mode.
The workaround is to select stacked mode in this configuration.
Change-Id: I6f37ce15a4e98a4cdbd6d893f22846a65c8be021
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26564
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c
index 9e649b0..d41b74c 100644
--- a/src/northbridge/intel/x4x/raminit.c
+++ b/src/northbridge/intel/x4x/raminit.c
@@ -352,6 +352,26 @@
}
}
+/* With DDR3 and 533MHz mem clock and an enabled internal gfx device the display
+ is not usable in non stacked mode, so select stacked mode accordingly */
+static void workaround_stacked_mode(struct sysinfo *s)
+{
+ u32 deven;
+ /* Only a problem on DDR3 */
+ if (s->spd_type == DDR2)
+ return;
+ /* Does not matter if only one channel is populated */
+ if (!CHANNEL_IS_POPULATED(s->dimms, 0)
+ || !CHANNEL_IS_POPULATED(s->dimms, 1))
+ return;
+ if (s->selected_timings.mem_clk != MEM_CLOCK_1066MHz)
+ return;
+ /* IGD0EN gets disabled if not present before this code runs */
+ deven = pci_read_config32(PCI_DEV(0, 0, 0), D0F0_DEVEN);
+ if (deven & IGD0EN)
+ s->stacked_mode = 1;
+}
+
static int ddr3_save_dimminfo(u8 dimm_idx, u8 *raw_spd,
struct abs_timings *saved_timings, struct sysinfo *s)
{
@@ -544,6 +564,7 @@
else
select_cas_dramfreq_ddr3(s, &saved_timings);
select_discrete_timings(s, &saved_timings);
+ workaround_stacked_mode(s);
}
static void find_dimm_config(struct sysinfo *s)