commit 59e03ebf4cd5f4b1cbf5f6ff6281d372e519e6a6
author Tim Crawford <tcrawford@system76.com> Wed May 18 16:00:34 2022 -0600
committer Felix Held <felix-coreboot@felixheld.de> Thu Jul 14 23:09:32 2022 +0000
tree fddc587ca9d916657b0736a7e2fb86e61bead081
parent 44ef2123b05eb4f5f8d5578f1b0b2fd70d9507a9

mb/system76: TGL-U: Disable AER for CPU PCIe RP

Disable PCIe Advanced Error Reporting on the CPU root port to prevent
some SSDs from timing out on S0ix suspend. AER results in the drive not
being able to switch from D3 back to D0.

    nvme 0000:01:00.0: can't change power state from D3cold to D0 (config space inaccessible)

Known to affect at least the following SSD models:

- ADATA XPG SX8200 Pro
- Samsung 970 EVO Plus (FW version: 2B7QCXE7)

Change-Id: I79da6b08ef1949f3bf1c6111aaa7e658bd29c0e2
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64080
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/system76/darp7/ramstage.c

diff --git a/src/mainboard/system76/darp7/ramstage.c b/src/mainboard/system76/darp7/ramstage.c
index a3b12bb..dd7e73c 100644
--- a/src/mainboard/system76/darp7/ramstage.c
+++ b/src/mainboard/system76/darp7/ramstage.c
@@ -3,6 +3,12 @@
 #include <mainboard/gpio.h>
 #include <soc/ramstage.h>
 
+void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+{
+	// Disable AER to fix suspend failing with some SSDs.
+	params->CpuPcieRpAdvancedErrorReporting[0] = 0;
+}
+
 static void mainboard_init(void *chip_info)
 {
 	mainboard_configure_gpios();

src/mainboard/system76/galp5/ramstage.c

diff --git a/src/mainboard/system76/galp5/ramstage.c b/src/mainboard/system76/galp5/ramstage.c
index dec2a89..e2cbba5 100644
--- a/src/mainboard/system76/galp5/ramstage.c
+++ b/src/mainboard/system76/galp5/ramstage.c
@@ -3,6 +3,12 @@
 #include <soc/ramstage.h>
 #include "gpio.h"
 
+void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+{
+	// Disable AER to fix suspend failing with some SSDs.
+	params->CpuPcieRpAdvancedErrorReporting[0] = 0;
+}
+
 static void mainboard_init(void *chip_info)
 {
 	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));

src/mainboard/system76/lemp10/ramstage.c

diff --git a/src/mainboard/system76/lemp10/ramstage.c b/src/mainboard/system76/lemp10/ramstage.c
index a3b12bb..dd7e73c 100644
--- a/src/mainboard/system76/lemp10/ramstage.c
+++ b/src/mainboard/system76/lemp10/ramstage.c
@@ -3,6 +3,12 @@
 #include <mainboard/gpio.h>
 #include <soc/ramstage.h>
 
+void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+{
+	// Disable AER to fix suspend failing with some SSDs.
+	params->CpuPcieRpAdvancedErrorReporting[0] = 0;
+}
+
 static void mainboard_init(void *chip_info)
 {
 	mainboard_configure_gpios();