diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c
index 59a384a..47d595c 100644
--- a/src/southbridge/intel/ibexpeak/azalia.c
+++ b/src/southbridge/intel/ibexpeak/azalia.c
@@ -10,10 +10,6 @@
 #include <device/azalia_device.h>
 #include "pch.h"
 
-#define HDA_ICII_REG 0x68
-#define HDA_ICII_BUSY (1 << 0)
-#define HDA_ICII_VALID (1 << 1)
-
 static int set_bits(void *port, u32 mask, u32 val)
 {
 	u32 reg32;
@@ -48,15 +44,15 @@
 	u8 reg8;
 
 	/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
-	if (set_bits(base + 0x08, 1, 1) == -1)
+	if (set_bits(base + HDA_GCTL_REG, 1, 1) == -1)
 		goto no_codec;
 
 	/* Write back the value once reset bit is set. */
-	write16(base + 0x0,
-		read16(base + 0x0));
+	write16(base + HDA_GCAP_REG,
+		read16(base + HDA_GCAP_REG));
 
 	/* Read in Codec location (BAR + 0xe)[2..0]*/
-	reg8 = read8(base + 0xe);
+	reg8 = read8(base + HDA_STATESTS_REG);
 	reg8 &= 0x0f;
 	if (!reg8)
 		goto no_codec;
@@ -66,7 +62,7 @@
 no_codec:
 	/* Codec Not found */
 	/* Put HDA back in reset (BAR + 0x8) [0] */
-	set_bits(base + 0x08, 1, 0);
+	set_bits(base + HDA_GCTL_REG, 1, 0);
 	printk(BIOS_DEBUG, "Azalia: No codec!\n");
 	return 0;
 }
@@ -155,14 +151,14 @@
 	}
 
 	reg32 = (addr << 28) | 0x000f0000;
-	write32(base + 0x60, reg32);
+	write32(base + HDA_IC_REG, reg32);
 
 	if (wait_for_valid(base) == -1) {
 		printk(BIOS_DEBUG, "  codec not valid.\n");
 		return;
 	}
 
-	reg32 = read32(base + 0x64);
+	reg32 = read32(base + HDA_IR_REG);
 
 	/* 2 */
 	printk(BIOS_DEBUG, "Azalia: codec viddid: %08x\n", reg32);
@@ -179,7 +175,7 @@
 		if (wait_for_ready(base) == -1)
 			return;
 
-		write32(base + 0x60, verb[i]);
+		write32(base + HDA_IC_REG, verb[i]);
 
 		if (wait_for_valid(base) == -1)
 			return;
@@ -199,7 +195,7 @@
 		if (wait_for_ready(base) == -1)
 			return;
 
-		write32(base + 0x60, pc_beep_verbs[i]);
+		write32(base + HDA_IC_REG, pc_beep_verbs[i]);
 
 		if (wait_for_valid(base) == -1)
 			return;
@@ -268,9 +264,9 @@
 	/* Codec Initialization Programming Sequence */
 
 	/* Take controller out of reset */
-	reg32 = read32(base + 0x08);
-	reg32 |= (1 << 0);
-	write32(base + 0x08, reg32);
+	reg32 = read32(base + HDA_GCTL_REG);
+	reg32 |= HDA_GCTL_CRST;
+	write32(base + HDA_GCTL_REG, reg32);
 	/* Wait 1ms */
 	udelay(1000);