soc/amd/stoneyridge/northbridge: report GNB IOAPIC in domain
Move the GNB IOAPIC resource from being reported in the GNB PCI device
to the domain and use IOMMU_IOAPIC_IDX as resource index, so that the
common AMD MADT code will be able to find the resource.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If6e9aaf4a3fa2c5b0266fd9fb8254285f8555317
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c
index bf2f992..2b6ba45 100644
--- a/src/soc/amd/stoneyridge/northbridge.c
+++ b/src/soc/amd/stoneyridge/northbridge.c
@@ -43,9 +43,6 @@
* the CPU_CLUSTER.
*/
mmconf_resource(dev, idx++);
-
- /* NB IOAPIC2 resource */
- mmio_range(dev, idx++, IO_APIC2_ADDR, 0x1000);
}
/**
@@ -301,6 +298,10 @@
/* Low top usable RAM -> Low top RAM (bottom pci mmio hole) */
reserved_ram_from_to(dev, idx++, mem_useable, tom);
+ /* NB IOAPIC2 resource. IOMMU_IOAPIC_IDX is used as index, so that the common AMD MADT
+ code can find this resource */
+ mmio_range(dev, IOMMU_IOAPIC_IDX, IO_APIC2_ADDR, 0x1000);
+
/* If there is memory above 4GiB */
if (high_tom >> 32) {
/* 4GiB -> high top usable */